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Libraries Guide
Chapter 9: Design Elements (PULLDOWN to ROM32X1)

RAM16X4S

16-Deep by 4-Wide Static Synchronous RAM

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Spartan2
Virtex
N/A
Macro
Macro
N/A
N/A
Macro
Macro
Macro
Macro

RAM16X4S is a 16-word by 4-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D3 - D0) into the word selected by the 4-bit address (A3 - A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pin (O3 - O0) is the data that is stored in the RAM at the location defined by the values on the address pins.

The initial contents of RAM16X4S cannot be specified directly. Initial contents may be specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying Initial Contents of a RAM” in the “RAM16X1” section.

Mode selection is shown in the following truth table.

Inputs
Outputs
WE (mode)
WCLK
D3 - D0
O3 - O0
0 (read)
X
X
Data
1 (read)
0
X
Data
1 (read)
1
X
Data
1 (write)

D3-D0
D3-D0
1 (read)

X
Data
Data = word addressed by bits A3 - A0