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Libraries Guide
Chapter 9: Design Elements (PULLDOWN to ROM32X1)

RAM16X1S_1

16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Spartan2
Virtex
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Primitive
Primitive

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 4-bit address (A3 - A0). For predictable performance, address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins.

You can initialize RAM16X1S_1 during configuration. See “Specifying Initial Contents of a RAM” in the “RAM16X1” section.

Mode selection is shown in the following truth table.

Inputs
Outputs
WE(mode)
WCLK
D
O
0 (read)
X
X
Data
1 (read)
0
X
Data
1 (read)
1
X
Data
1 (write)

0
D
1 (read)

X
Data
Data = word addressed by bits A3 - A0