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This section includes recommendations for compiling your designs to improve your results and decrease the run time.
Note: Refer to your synthesis tool documentation for more information on compilation options and suggestions.
Before you can compile your design, you must create an initialization file to specify compiler defaults, and to point to the applicable implementation libraries. Refer to your synthesis tool documentation for information on creating this file.
The next step is to create a compile run script for iterative design compilations, and to use as a reference for the steps in the synthesis process. Many commonly-used synthesis tools have this capability. If you are a new user, you may want to use the graphical user interface to compile your design instead of using a run script. However, the iterative design compilation process can be tedious with the graphical interface. A run script can speed up the design process.
Use the recommendations in this section to successfully compile your design.
You may need to modify your code to successfully compile your design because certain design constructs that are effective for simulation may not be as effective for synthesis. The synthesis syntax and code set may differ slightly from the simulator syntax and code set.
Older versions of synthesis tools required incremental design compilations to decrease run times. Some or all levels of hierarchy were compiled with separate compile commands and saved as output or database files. The output netlist or compiled database file for each module was read during synthesis of the top level code. This method is not necessary with new synthesis tools, which can handle large designs from the top down. The 5,000 gates per module rule of thumb no longer applies with the new synthesis tools. Refer to your synthesis tool documentation for details.
After your design is successfully compiled, save it as an XNF or EDIF file for input to the Xilinx software.