Implementing Multiplexers with Tristate Buffers

A 4-to-1 multiplexer is efficiently implemented in a single XC4000 or Spartan family CLB. The six input signals (four inputs, two select lines) use the F, G, and H function generators. Multiplexers that are larger than 4-to-1 exceed the capacity of one CLB. For example, a 16-to-1 multiplexer requires five CLBs and has two logic levels. These additional CLBs increase area and delay. Xilinx recommends that you use internal tristate buffers (BUFTs) to implement large multiplexers.

Large multiplexers built with BUFTs have the following advantages.

• Can vary in width with only minimal impact on area and delay
  
  
• Can have as many inputs as there are tristate buffers per horizontal longline in the target device
  
  
• Have one-hot encoded selector inputs
  
  

This last point is illustrated in the following VHDL and Verilog designs of a 5-to-1 multiplexer built with gates. Typically, the gate version of this multiplexer has binary encoded selector inputs and requires three select inputs (SEL<2:0>). The schematic representation of this design is shown in the “5-to-1 MUX Implemented with Gates” figure.

Some synthesis tools include commands that allow you to switch between multiplexers with gates or with tristates. Check with your synthesis vendor for more information.

The VHDL and Verilog designs provided at the end of this section show a 5-to-1 multiplexer built with tristate buffers. The tristate buffer version of this multiplexer has one-hot encoded selector inputs and requires five select inputs (SEL<4:0>). The schematic representation of these designs is shown in the “5-to-1 MUX Implemented with BUFTs” figure.

Mux Implemented with Gates VHDL Example

-- MUX_GATE.VHD

-- 5-to-1 Mux Implemented in Gates

-- May 1997                        



library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;



entity mux_gate is

port (SEL: in STD_LOGIC_VECTOR (2 downto 0);

A,B,C,D,E: in STD_LOGIC;

        SIG: out STD_LOGIC);

end mux_gate;



architecture RTL of mux_gate is

begin

    SEL_PROCESS: process (SEL,A,B,C,D,E)

    begin

        case SEL is

           when "000"  => SIG <= A;

           when "001"  => SIG <= B;

           when "010"  => SIG <= C;

           when "011"  => SIG <= D;

           when others => SIG <= E;

        end case;

    end process SEL_PROCESS;

end RTL;

Mux Implemented with Gates Verilog Example

/* MUX_GATE.V

 * May 1997 */



module mux_gate (A,B,C,D,E,SEL,SIG);



input A,B,C,D,E;

input [2:0] SEL;

output SIG;

reg SIG;



    always @ (A or B or C or D or SEL) 

    case (SEL)

        3'b000: 

            SIG=A;

        3'b001: 

            SIG=B;

        3'b010: 

            SIG=C;

        3'b011: 

            SIG=D;

        3'b100: 

            SIG=E;

default: SIG=A;

     endcase



endmodule

Figure 4.9 5-to-1 MUX Implemented with Gates

Mux Implemented with BUFTs VHDL Example

-- MUX_TBUF.VHD

-- 5-to-1 Mux Implemented in 3-State Buffers

-- May 1997                        



library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;



entity mux_tbuf is

port (SEL: in STD_LOGIC_VECTOR (4 downto 0);

A,B,C,D,E: in STD_LOGIC;

        SIG: out STD_LOGIC);

end mux_tbuf;



architecture RTL of mux_tbuf is

begin



    SIG <= A when (SEL(0)='0') else 'Z';

    SIG <= B when (SEL(1)='0') else 'Z';

    SIG <= C when (SEL(2)='0') else 'Z';

    SIG <= D when (SEL(3)='0') else 'Z';

    SIG <= E when (SEL(4)='0') else 'Z';



end RTL;

Mux Implemented with BUFTs Verilog Example

/* MUX_TBUF.V

 * May 1997 */



module mux_tbuf (A,B,C,D,E,SEL,SIG);



input A,B,C,D,E;

input [4:0] SEL;

output SIG;

reg SIG;



    always @ (SEL or A) 

    begin

        if (SEL[0]==1'b0) 

            SIG=A;

        else

            SIG=1'bz;

     end



     always @ (SEL or B) 

     begin

         if (SEL[1]==1'b0)

             SIG=B;

         else

             SIG=1'bz;

         end



     always @ (SEL or C) 

     begin

         if (SEL[2]==1'b0)

             SIG=C;

         else 

             SIG=1'bz;

     end



     always @ (SEL or D) 

     begin

         if (SEL[3]==1'b0)

              SIG=D;

         else

              SIG=1'bz;

         end



     always @ (SEL or E) 

     begin

         if (SEL[4]==1'b0)

              SIG=E;

         else

              SIG=1'bz;

         end



endmodule

Figure 4.10 5-to-1 MUX Implemented with BUFTs

A comparison of timing and area for a 5-to-1 multiplexer built with gates and tristate buffers in an XC4005EPC84-2 device is provided in the following table. When the multiplexer is implemented with tristate buffers, no CLBs are used and the delay is smaller.

Table 4_5 Timing/Area for 5-to-1 MUX (XC4005EPC84-2)