|
|
|
|
|
Note: Refer to the Development System Reference Guide for a detailed description of the XC4000/XC5200 boundary scan capabilities.
XC4000, Spartan, and XC5200 FPGAs contain boundary scan facilities that are compatible with IEEE Standard 1149.1. Xilinx devices support external (I/O and interconnect) testing and have limited support for internal self-test.
You can access the built-in boundary scan logic between power-up and the start of configuration. Optionally, the built-in logic is available after configuration if you specify boundary scan in your design. During configuration, a reduced boundary scan capability (sample/preload and bypass instructions) is available.
In a configured FPGA device, the boundary scan logic is enabled or disabled by a specific set of bits in the configuration bitstream. To access the boundary scan logic after configuration in HDL designs, you must instantiate the boundary scan symbol, BSCAN, and the boundary scan I/O pins, TDI, TMS, TCK, and TDO.
The XC5200 BSCAN symbol contains three additional pins: RESET, UPDATE, and SHIFT, which are not available for XC4000 and Spartan. These pins represent the decoding of the corresponding state of the boundary scan internal state machine. If this function is not used, you can leave these pins unconnected in your HDL design.
To incorporate the boundary scan capability in a configured FPGA using synthesis tools, you must manually instantiate boundary scan library primitives at the source code level. These primitives include TDI, TMS, TCK, TDO, and BSCAN. The following VHDL and Verilog examples show how to instantiate the boundary scan symbol, BSCAN, into your HDL code. Note that the boundary scan I/O pins are not declared as ports in the HDL code. The schematic for this design is shown in the “Bnd_scan Schematic” figure.
You must assign a Set Don't Touch or equivalent attribute to the net connected to the TDO pad before using the Insert Pads (or equivalent) and compile commands. Otherwise, the TDO pad is removed by the compiler. In addition, you do not need IBUFs or OBUFs for the TDI, TMS, TCK, and TDO pads. These special pads connect directly to the Xilinx boundary scan module.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity bnd_scan is
port (TDI_P, TMS_P, TCK_P : in STD_LOGIC;
LOAD_P, CE_P, CLOCK_P, RESET_P: in
STD_LOGIC;
DATA_P: in STD_LOGIC_VECTOR(3 downto 0);
TDO_P: out STD_LOGIC;
COUT_P: out STD_LOGIC_VECTOR(3 downto 0));
end bnd_scan;
architecture XILINX of bnd_scan is
component BSCAN
port (TDI, TMS, TCK out STD_LOGIC;
TDO: in STD_LOGIC);
end component;
component TDI
port (I: out STD_LOGIC);
end component;
component TMS
port (I: out STD_LOGIC);
end component;
component TCK
port (I: out STD_LOGIC);
end component;
component TDO
port (O: out STD_LOGIC);
end component;
component count4
port (LOAD, CE, CLOCK, RST: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR (3 downto 0);
COUT: out STD_LOGIC_VECTOR (3 downto 0));
end component;
-- Defining signals to connect BSCAN to Pins --
signal TCK_NET : STD_LOGIC;
signal TDI_NET : STD_LOGIC;
signal TMS_NET : STD_LOGIC;
signal TDO_NET : STD_LOGIC;
begin
U1: BSCAN port map (TDO => TDO_NET,
TDI => TDI_NET,
TMS => TMS_NET,
TCK => TCK_NET);
U2: TDI port map (I =>TDI_NET);
U3: TCK port map (I =>TCK_NET);
U4: TMS port map (I =>TMS_NET);
U5: TDO port map (O =>TDO_NET);
U6: count4 port map (LOAD => LOAD_P,
CE => CE_P,
CLOCK => CLOCK_P,
RST => RESET_P,
DATA => DATA_P,
COUT => COUT_P);
end XILINX;
/////////////////////////////////////////////////////
// BND_SCAN.V //
// Example of instantiating the BSCAN symbol in //
// activating the Boundary Scan circuitry //
// Count4 is an instantiated .v file of a counter //
// September 1997 //
/////////////////////////////////////////////////////
module bnd_scan (LOAD_P, CLOCK_P, CE_P, RESET_P,
DATA_P, COUT_P);
input LOAD_P, CLOCK_P, CE_P, RESET_P;
input [3:0] DATA_P;
output [3:0] COUT_P;
wire TDI_NET, TMS_NET, TCK_NE, TDO_NET;
BSCAN U1 (.TDO(TDO_NET), .TDI(TDI_NET), .TMS(TMS_NET), .TCK(TCK_NET));
TDI U2 (.I(TDI_NET));
TCK U3 (.I(TCK_NET));
TMS U4 (.I(TMS_NET));
TDO U5 (.O(TDO_NET));
count4 U6 (.LOAD(LOAD_P), .CLOCK(CLOCK_P), .CE(CE_P),
.RST(RESET_P), .DATA(DATA_P), .COUT(COUT_P));
endmodule
Figure 4.7 Bnd_scan Schematic