TRACE Output Details

TRACE output is an ASCII timing report file that enables you to see how well the timing constraints for the design have been met. The file is written into your current working directory and has a .twr extension. The default name for the file is the same root name as the NCD file. You can designate a different root name for the file, but it must have a .twr extension. The extension .twr is assumed if not specified.

The timing report lists statistics on the design, any detected timing errors, and a number of warning conditions.

Timing errors indicate absolute or relative timing constraint violations. These include the following.

Path delay errors - where the path delay exceeds the maximum delay constraint for a path.
Net delay errors - where a net connection delay exceeds the maximum delay constraint for the net.
Offset errors - where either the delay offset between an external clock and its associated data-in pin is insufficient to meet the internal logic's timing requirements or the delay offset between an external clock and its associated data-out pin exceeds the external logic's timing requirements.
Net skew errors - where skew between net connections exceeds the maximum skew constraint for the net.

Timing errors may require design modifications, running PAR, or both.

Warnings point out potential problems such as circuit loops or a constraint that does not define any paths.

Three types of reports are available. You determine the report type by entering the appropriate option entry on the UNIX or DOS command line or by selecting the type of report from the Timing Analyzer (see the “TRACE Options” section). Each type of report is described in the “Reporting with TRACE” section.

Timing Verification with TRACE

TRACE checks the delays in the NCD design file against your timing constraints. If delays are exceeded, TRACE issues the appropriate timing error.

Net Delay Constraints

The delay for a constrained net is checked to ensure that the constraint is equal to or greater than the routedelay.

constraint >= routedelay

routedelay is the signal delay between the driver pin and the load pin(s) on a net. This is an estimated delay if the design is placed but not routed.

Any nets showing delays that do not meet this condition generate timing errors in the timing report.

Net Skew Constraints

Signal skew on a net with multiple load pins is the difference between minimum and maximum load delays. Skew is checked against the specified maximum skew for constrained nets in the PCF file.

constraint >= (maxdelay - mindelay)

maxdelay is the maximum delay between the driver pin and a load pin.

mindelay is the minimum delay between the driver pin and a load pin.

If the skew is found to exceed the maximum skew constraint, the timing report shows a skew error.

Path Delay Constraints

The delay through a constrained path is checked to ensure that the constraint is greater than or equal to the sum of logic (component) delay, route (wire) delay, and setup time (if any), minus clock skew (if any).

constraint >= logicdelay + routedelay + setuptime - clockskew

logicdelay is the pin-to-pin delay through a component.

routedelay is the signal delay between component pins in a path. This is an estimated delay if the design is placed but not routed.

setuptime (for clocked paths only) is the time that data must be present on an input pin before the arrival of the triggering edge of a clock signal.

clockskew (for register-to-register clocked paths only) is the difference between the amount of time the clock signal takes to reach the destination register and the amount of time the clock signal takes to reach the source register. Clock skew is discussed in the following section.

Paths showing delays that do not meet this condition generate timing errors in the timing report.

Clock Skew and Setup Checking

Clock skew must be accounted for in register-to-register setup checks. For register-to-register paths, the data delay must reach the destination register within a single clock period for the destination register. The timing analysis software ensures that any clock skew between the source and destination registers is accounted for in this check.

NOTE

In default mode, that is, without using the -skew option, only dedicated clock resource skew accounting is performed. With the
-skew option, non-dedicated clock skew accounting is also performed.

A setup check performed on register-to-register paths checks the following condition.

Slack = constraint + Tsk (Tpath + Tsu)

constraint is the required time interval for the path, either specified explicitly by you with a FROM:TO constraint, or derived from a PERIOD constraint.

Tpath is the summation of component and connection delays along the path (including the Tcko delay from the source register).

Tsu is the setup requirement for the destination register.

Tsk is the difference between the arrival time for the destination register and the source register.

Negative slack indicates that a setup error may occur, because the data from the source register does not set up at the target register for a subsequent clock edge.

In the following figure, the clock skew Tsk is the delay from the clock input (CLKIOB) to register D (TclkD) less the delay from the clock input (CLKIOB) to register S (TclkS). Negative skew relative to the destination reduces the amount of time available for the data path, and positive skew relative to the destination register is truncated to zero.

Figure 12.4 Clock Skew Example

Because the total clock path delay is used to determine the clock arrival times at the source register (TclkS) and the destination register (TclkD), this check still applies if the source and destination clocks originate at the same chip input but travel through different clock buffers and/or routing resources, as shown in the following figure.

Figure 12.5 Clock Passing Through Multiple Buffers

When the source and destination clocks originate at different chip inputs, no obvious relationship between the two clock inputs exists for the timing software (because the software cannot determine the clock arrival time or phase information).

For FROM:TO specifications, the software assumes you have taken into account the external timing relationship between the chip inputs. The software assumes both clock inputs arrive simultaneously, and the difference between the destination clock arrival time (TclkD) and the source clock arrival time (TclkS) does not account for any difference in the arrival times at the two chip clock inputs.

Figure 12.6 Clocks Originating at Different Chip Inputs

The clock skew Tsk is not accounted for in setup checks covered by PERIOD constraints where the clock paths to the source and destination registers originate at different clock inputs.

Reporting with TRACE

The timing report produced by TRACE is an ASCII file prepared for a particular design. It reports statistics on the design, a summary of timing warnings and errors, and optional detailed net and path delay reports.

NOTE

All TRACE reports are formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the reports uses a proportional font, the columns in the reports do not line up correctly.

This section covers the three different types of timing reports generated by TRACE. They are as follows.

The summary report - Contains summary information, design statistics, and statistics for each constraint in the PCF file.
The error report - Lists timing errors and associated net/path delay information.
The verbose report - Lists delay information for all nets and paths.

In each type of report, the header specifies the type of report, the input design name, the optional input physical constraints file name, and device and speed data for the input NCD file. At the end of each report is a timing summary, which includes the following information.

The number of timing errors found in the design. This information appears in all reports
A timing score, showing the total amount of error (in picoseconds) for all timing constraints in the design
The number of paths and nets covered by the constraints
The number of route delays and the percentage of connections covered by timing constraints

NOTE
The percentage of connections covered by timing constraints is given in a “% coverage” statistic. The statistic does not indicate the percentage of paths covered; it indicates the percentage of connections covered. Even if you have entered constraints that cover all paths in the design, this percentage may be less than 100%, since some connections are never included for timing analysis (for example, connections to the STARTUP component).
The number of nets covered by constraints

A list of global statistics for the design

In the following sections, a description of each report is accompanied by a sample.

Following are some additional notes about timing reports.

For any of the three types of reports, if you specify a physical constraints file that contains invalid data, a list of physical constraints file errors appears at the beginning of the report. These include errors in constraint syntax.
In a TRACE report, a tilde (~) preceding a delay value indicates that the delay value is approximate. Values with the tilde cannot be calculated exactly because of excessive delays, resistance, or capacitance on the net, that is, the path is too complex too calculate accurately.

The tilde (~) also means that the path may exceed the numerical value listed next to the tilde by as much as 20%. You can use the PENALIZE TILDE constraint to penalize these delays by a specified percentage (see the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide for a description of the PENALIZE TILDE constraint).
In a TRACE report, an “R” appended to a delay value indicates the value was calculated for a rising signal, and an “F” indicates the value for a falling signal. If rising and falling values are different, TRACE reports the appropriate delay.
TRACE detects when a path loops (that is, when the path passes through a driving output more than once), and reports the total number of loops detected in the design. When TRACE detects a loop, it disables the loop from being analyzed. If the loop itself is made up of many possible routes, each route is disabled for all paths which converge through the loop in question and the total number is included in the reported loop tally.

A path is considered to loop outside of the influence of other paths in the design. Thus if a valid path follows a loop from another path, but actually converges at an input and not a driving output, the path is not disabled and will contain the elements of the loop which may be disabled on another path.
In Xilinx FPGAs, tristate buffer (TBUF) outputs are always routed on longlines. Pullup resistors may also be tied to these longlines. The timing effects of a TBUF/pullup combination is handled differently in the various FPGA architectures.
- In XC3000A/L, XC3100A/L, 4000E/L, XC5200, and Spartan designs, the delay associated with the longline is built into the component delay for the TBUF, and is not included in the delay reported for the net on the longline.
- In XC4000EX/XL/XV designs, the net delay on the longline is computed and reported as if the pullup (and not the TBUF output) is driving the net. If you want the delay to be computed with the TBUF driving the net, do not include any pullups at the output of the TBUF.

For Release 1.5, if you are using the new default connection-based analysis method instead of the DFS option, error counts reflect the number of path endpoints (register setup inputs, output pads) that fail to meet timing specifications, not the number of paths that fail the specification. Consider the following circuit.

Figure 12.7 Error Reporting

Assume that you are using the new connection-based analysis method. If an error is generated at both the endpoints of A and B, the timing report would list two errors - one for each endpoint.

If you are using the -dfs option, the timing report would list ten errors, that is, the report would list the paths instead of the endpoints.

Summary Report

The summary report includes the name of the design file being analyzed, the device speed and report level, followed by a statistical brief that includes the summary information (timing errors, etc. described above) and design statistics. The report also list statistics for each constraint in the PCF file, including the number of timing errors for each constraint.

A summary report is produced when you do not enter an -e (error report) or -v (verbose report) option on the TRACE command line.

Two sample summary reports are shown below. The first sample shows the results without having a physical constraints file. The second sample shows the results when a physical constraints file is specified.

If no physical constraints file exists or if there are no timing constraints in the PCF file, TRACE performs default path and net enumeration to provide timing analysis statistics. Default path enumeration includes all circuit paths to data and clock pins on sequential components and all data pins on primary outputs. Default net enumeration includes all nets.

NOTE

The summary report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

Summary Report (Without a Physical Constraints File Specified)

The following sample summary report represents the output of this TRACE command.

trce -o summary1.twr trace1.ncd

The name of the report is summary1.twr. No preference file is specified on the command line, and the directory containing the file trace1.ncd did not contain a PCF file called trace1.pcf.

Xilinx TRACE, Version M1.5.15
   Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
   
   Design file:              trace1.ncd
   Device,speed:             xc4028ex,-3 (x1_0.28 1.8 PRELIMINARY)
   Report level:             summary report
   -------------------------------------------------------------------------
   
   WARNING:bastw:170 - No timing constraints found, doing default enumeration.
   
   -------------------------------------------------------------------------
     Constraint                                | Requested  | Actual     | Logic 
                                               |            |            | Levels
   -------------------------------------------------------------------------
     Default period analysis                   |            | 32.913ns   |      
   -------------------------------------------------------------------------
     Default net enumeration                   |            | 22.769ns   |      
   -------------------------------------------------------------------------
   
   All constraints were met.
   
   Timing summary:
   ---------------
   
   Timing errors: 0  Score: 0
   
   Constraints cover 1662 paths, 261 nets, and 836 connections (100.0% coverage)

Design statistics:
      Minimum period:  32.913ns (Maximum frequency:  30.383MHz)
      Maximum combinational path delay:  67.491ns
      Maximum net delay:  22.769ns


Analysis completed Tue Apr 28 13:56:52 1998
   -------------------------------------------------------------------------

Summary Report (With a Physical Constraints File Specified)

The following sample summary report represents the output of this TRACE command.

trce -o summary.twr trace1.ncd trace1.pcf

The name of the report is summary.twr. The timing analysis represented in the file were performed by referring to the constraints in the file trace1.pcf.

-------------------------------------------------------------------------
Xilinx TRACE, Version M1.5.15
   Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
   
   Design file:              trace1.ncd
   Physical constraint file: trace1.pcf
   Device,speed:             xc4028ex,-3 (x1_0.28 1.8)
   Report level:             summary report
   -------------------------------------------------------------------------
   
   
   -------------------------------------------------------------------------
     Constraint                                | Requested  | Actual     | Logic 
                                               |            |            | Levels
   -------------------------------------------------------------------------
     NET "CTLR/2SCLK" PERIOD = 43.000000 nS    | 43.000ns   | 32.913ns   | 2    
   -------------------------------------------------------------------------
     NET "CTLR/SCLK" PERIOD = 45.000000 nS     | 45.000ns   | 30.140ns   | 5    
   -------------------------------------------------------------------------

All constraints were met.

Timing summary:
   ---------------
   
   Timing errors: 0  Score: 0

Constraints cover 1459 paths, 0 nets, and 631 connections (75.5% coverage)

Design statistics:
      Minimum period:  32.913ns (Maximum frequency: 30.383MHz)
   
   Analysis completed Tue Apr 28 13:52:20 1998

   -------------------------------------------------------------------------

When the physical constraints file includes timing constraints, the summary report lists the percentage of all design connections covered by timing constraints. If there are no timing constraints, the report shows 100 percent coverage. An asterisk precedes constraints that fail.

Error Report

The error report lists timing errors and associated net/path delay information. Errors are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). The number of errors listed for each constraint is set by the limit you enter on the command line. The error report also contains a list of all time groups defined in the PCF file and all of the members defined within each group.

The main body of the error report lists all timing constraints as they appear in the input PCF file. If the constraint is met, the report simply states the number of items scored by TRACE, reports no timing errors detected, and issues a brief report line, indicating important information (for example, the maximum delay for the particular constraint). If the constraint is not met, it gives the number of items scored by TRACE, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical resource and the logical resource from which the physical resource was generated.

As in the other three types of reports, descriptive material appears at the top. A timing summary always appears at the end of the report. A sample error report follows.

NOTE

The error report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

Sample Error Report

The following sample error report (error.twr) represents the output of this TRACE command.

trce -o error2.twr -e 2 trace2.ncd trace2.pcf

Xilinx TRACE, Version M1.5.15
   Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
   
   Design file:              trace2.ncd
   Physical constraint file: trace2.pcf
   Device,speed:             xc4028ex,-3 (x1_0.28 1.8)
   Report level:             error report, limited to 2 items per constraint
   -------------------------------------------------------------------------

=========================================================================
Timing constraint: NET "CTLR/2SCLK" PERIOD = 30.000000 nS ;
   294 items analyzed, 1 timing error detected.
    Minimum period is  32.913ns.
   -------------------------------------------------------------------------
   Slack:    -2.913ns path CTLR/ODM/FBYT0 to RD_EN_O- relative to
             30.000ns delay constraint

Path CTLR/ODM/FBYT0 to RD_EN_O- contains 7 levels of logic:
   Path starting from Comp: CLB_R14C13.K (from CTLR/2SCLK)
   To                   Delay type         Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  --------
   CLB_R14C13.XQ        Tcko                  1.830R  CTLR/ODM/FBYT0
                                                      CTLR/ODM/FBYTCNTR/Q0
   CLB_R15C11.F4        net (fanout=8)        2.150R  CTLR/ODM/FBYT0
   CLB_R15C11.Y         Tiho                  3.100R  CTLR/ODM/FBYT_TC
                                                      CTLR/ODM/FBYTCNTR/TC
   CTLR/ODM/LD0/CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.F3        net (fanout=1)        1.515R  CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.Y         Tiho                  3.100R  CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/LD0/CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/VBYTCNTR/M0P/$1I5
   CLB_R15C12.F1        net (fanout=1)        1.238R  CTLR/ODM/VBYTCNTR/M0P
   CLB_R15C12.X         Tilo                  1.700R  CTLR/ODM/VBYTCNTR/NS0
                                                      CTLR/ODM/VBYTCNTR/M0C/$1I5
   CLB_R17C21.F1        net (fanout=2)        5.015R  CTLR/ODM/VBYTCNTR/NS0
   CLB_R17C21.X         Tilo                  1.700R  CTLR/ODM/NS1-4

CTLR/ODM/ODM_SM/G11/CTLR/ODM/NS1-4
CLB_R19C29.F1        net (fanout=2)        3.723R  CTLR/ODM/NS1-4
   CLB_R19C29.Y         Tiho                  3.100R  CTLR/ODM/FIFOCTRL/RD_EN

CTLR/ODM/FIFOCTRL/G1/CTLR/ODM/FIFOCTRL/NS1-1-3-4
                                                   CTLR/ODM/FIFOCTRL/G6
   P126.O               net (fanout=1)        4.253R  CTLR/ODM/FIFOCTRL/RD_EN
   P126.OK              Took                  0.489R  RD_EN_O-
                                                      CTLR/ODM/FIFOCTRL/RD_EN
   -------------------------------------------------
   Total (15.019ns logic, 17.894ns route)    32.913ns (to CTLR/2SCLK)
         (45.6% logic, 54.4%% route)

-------------------------------------------------------------------------
Slack:    -2.871ns path CTLR/ODM/FBYT0 to RD_EN_O- relative to
             30.000ns delay constraint

Path CTLR/ODM/FBYT0 to RD_EN_O- contains 7 levels of logic:
   Path starting from Comp: CLB_R14C13.K (from CTLR/2SCLK)
   To                   Delay type         Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  --------
   CLB_R14C13.YQ        Tcko                  1.830R  CTLR/ODM/FBYT0
                                                      CTLR/ODM/FBYTCNTR/Q1
   CLB_R15C11.F3        net (fanout=8)        2.108R  CTLR/ODM/FBYT1
   CLB_R15C11.Y         Tiho                  3.100R  CTLR/ODM/FBYT_TC
                                                      CTLR/ODM/FBYTCNTR/TC
   CTLR/ODM/LD0/CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.F3        net (fanout=1)        1.515R  CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.Y         Tiho                  3.100R  CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/LD0/CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/VBYTCNTR/M0P/$1I5
   CLB_R15C12.F1        net (fanout=1)        1.238R  CTLR/ODM/VBYTCNTR/M0P
   CLB_R15C12.X         Tilo                  1.700R  CTLR/ODM/VBYTCNTR/NS0
                                                      CTLR/ODM/VBYTCNTR/M0C/$1I5
   CLB_R17C21.F1        net (fanout=2)        5.015R  CTLR/ODM/VBYTCNTR/NS0
   CLB_R17C21.X         Tilo                  1.700R  CTLR/ODM/NS1-4

CTLR/ODM/ODM_SM/G11/CTLR/ODM/NS1-4
CLB_R19C29.F1        net (fanout=2)        3.723R  CTLR/ODM/NS1-4
   CLB_R19C29.Y         Tiho                  3.100R  CTLR/ODM/FIFOCTRL/RD_EN

CTLR/ODM/FIFOCTRL/G1/CTLR/ODM/FIFOCTRL/NS1-1-3-4
                                                   CTLR/ODM/FIFOCTRL/G6
   P126.O               net (fanout=1)        4.253R  CTLR/ODM/FIFOCTRL/RD_EN
   P126.OK              Took                  0.489R  RD_EN_O-
                                                      CTLR/ODM/FIFOCTRL/RD_EN
   -------------------------------------------------
   Total (15.019ns logic, 17.852ns route)    32.871ns (to CTLR/2SCLK)
         (45.7% logic, 54.3%% route)

-------------------------------------------------------------------------

=========================================================================
Timing constraint: NET "CTLR/SCLK" PERIOD = 45.000000 nS ;
    1054 items analyzed, 0 timing errors detected.
    Minimum period is  30.140ns.
   -------------------------------------------------------------------------

1 constraint not met.

Timing summary:
   ---------------

Timing errors: 1  Score: 2913
   
   Constraints cover 1459 paths, 0 nets, and 631 connections (75.5% coverage)

Design statistics:
      Minimum period:  32.913ns (Maximum frequency:  30.383MHz)

Analysis completed Mon May 18 07:53:11 1998
   ------------------------------------------------------------------------

Verbose Report

The verbose report is similar to the error report, providing more details on delays for all constrained paths and nets in the design. Entries are ordered by constraint and, within constraints, by slack. The number of items listed for each constraint is set by the limit you enter on the command line.

The verbose report also contains a list of all time groups defined in the PCF file, and all of the members defined within each group.

As in the other types of reports, descriptive material appears at the top.

The body of the verbose report enumerates each constraint as it appears in the input physical constraints file, the number of items scored by TRACE for that constraint, and the number of errors detected for the constraint. Each item is described, ordered by descending slack. A Report line for each item provides important information, such as the amount of delay on a net and by how much the constraint is met.

For path constraints, if there is an error, the report indicates the amount by which the constraint is exceeded. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical resource and the logical resource from which the physical resource was generated.

If there are no errors, the report indicates that the constraint passed and by how much. Each logic and route delay is analyzed, totaled, and reported.

NOTE

The verbose report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

Sample Verbose Report

The following sample verbose report (verbose.twr) represents the output of this TRACE command.

trce -o verbose.twr -v 2 trace1.ncd trace1.pcf

-------------------------------------------------------------------------
Xilinx TRACE, Version M1.5.15
   Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Design file:              trace1.ncd
   Physical constraint file: trace1.pcf
   Device,speed:             xc4028ex,-3 (x1_0.28 1.8 PRELIMINARY)
   Report level:             verbose report, limited to 2 items per constraint
   -------------------------------------------------------------------------

=========================================================================
Timing constraint: NET "CTLR/2SCLK" PERIOD = 43.000000 nS ;
    294 items analyzed, 0 timing errors detected.
    Minimum period is  32.913ns.
   -------------------------------------------------------------------------
   Slack:    10.087ns path CTLR/ODM/FBYT0 to RD_EN_O- relative to
             43.000ns delay constraint

Path CTLR/ODM/FBYT0 to RD_EN_O- contains 7 levels of logic:
   Path starting from Comp: CLB_R14C13.K (from CTLR/2SCLK)
   To                   Delay type         Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  --------
   CLB_R14C13.XQ        Tcko                  1.830R  CTLR/ODM/FBYT0
                                                      CTLR/ODM/FBYTCNTR/Q0
   CLB_R15C11.F4        net (fanout=8)        2.150R  CTLR/ODM/FBYT0
   CLB_R15C11.Y         Tiho                  3.100R  CTLR/ODM/FBYT_TC
                                                      CTLR/ODM/FBYTCNTR/TC
   CTLR/ODM/LD0/CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.F3        net (fanout=1)        1.515R  CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.Y         Tiho                  3.100R  CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/LD0/CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/VBYTCNTR/M0P/$1I5
   CLB_R15C12.F1        net (fanout=1)        1.238R  CTLR/ODM/VBYTCNTR/M0P
   CLB_R15C12.X         Tilo                  1.700R  CTLR/ODM/VBYTCNTR/NS0
                                                      CTLR/ODM/VBYTCNTR/M0C/$1I5
   CLB_R17C21.F1        net (fanout=2)        5.015R  CTLR/ODM/VBYTCNTR/NS0
   CLB_R17C21.X         Tilo                  1.700R  CTLR/ODM/NS1-4
   CTLR/ODM/ODM_SM/G11/CTLR/ODM/NS1-4
   CLB_R19C29.F1        net (fanout=2)        3.723R  CTLR/ODM/NS1-4
   CLB_R19C29.Y         Tiho                  3.100R  CTLR/ODM/FIFOCTRL/RD_EN

CTLR/ODM/FIFOCTRL/G1/CTLR/ODM/FIFOCTRL/NS1-1-3-4
                                                   CTLR/ODM/FIFOCTRL/G6
   P126.O               net (fanout=1)        4.253R  CTLR/ODM/FIFOCTRL/RD_EN
   P126.OK              Took                  0.489R  RD_EN_O-
                                                      CTLR/ODM/FIFOCTRL/RD_EN
   -------------------------------------------------
   Total (15.019ns logic, 17.894ns route)    32.913ns (to CTLR/2SCLK)
         (45.6% logic, 54.4%% route)

-------------------------------------------------------------------------
Slack:    10.129ns path CTLR/ODM/FBYT0 to RD_EN_O- relative to
             43.000ns delay constraint

Path CTLR/ODM/FBYT0 to RD_EN_O- contains 7 levels of logic:
   Path starting from Comp: CLB_R14C13.K (from CTLR/2SCLK)
   To                   Delay type         Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  --------
   CLB_R14C13.YQ        Tcko                  1.830R  CTLR/ODM/FBYT0
                                                      CTLR/ODM/FBYTCNTR/Q1
   CLB_R15C11.F3        net (fanout=8)        2.108R  CTLR/ODM/FBYT1
   CLB_R15C11.Y         Tiho                  3.100R  CTLR/ODM/FBYT_TC
                                                      CTLR/ODM/FBYTCNTR/TC
   CTLR/ODM/LD0/CTLR/ODMLD_VBYT/2.0
   CLB_R16C11.F3        net (fanout=1)        1.515R  CTLR/ODM/LD_VBYT/2.0
   CLB_R16C11.Y         Tiho                  3.100R  CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/LD0/CTLR/ODM/LD_VBYT
                                                      CTLR/ODM/VBYTCNTR/M0P/$1I5
   CLB_R15C12.F1        net (fanout=1)        1.238R  CTLR/ODM/VBYTCNTR/M0P
   CLB_R15C12.X         Tilo                  1.700R  CTLR/ODM/VBYTCNTR/NS0
                                                      CTLR/ODM/VBYTCNTR/M0C/$1I5
   CLB_R17C21.F1        net (fanout=2)        5.015R  CTLR/ODM/VBYTCNTR/NS0
   CLB_R17C21.X         Tilo                  1.700R  CTLR/ODM/NS1-4

CTLR/ODM/ODM_SM/G11/CTLR/ODM/NS1-4
CLB_R19C29.F1        net (fanout=2)        3.723R  CTLR/ODM/NS1-4
   CLB_R19C29.Y         Tiho                  3.100R  CTLR/ODM/FIFOCTRL/RD_EN

CTLR/ODM/FIFOCTRL/G1/CTLR/ODM/FIFOCTRL/NS1-1-3-4
                                                   CTLR/ODM/FIFOCTRL/G6
   P126.O               net (fanout=1)        4.253R  CTLR/ODM/FIFOCTRL/RD_EN
   P126.OK              Took                  0.489R  RD_EN_O-
                                                      CTLR/ODM/FIFOCTRL/RD_EN
   -------------------------------------------------
   Total (15.019ns logic, 17.852ns route)    32.871ns (to CTLR/2SCLK)
         (45.7% logic, 54.3%% route)

-------------------------------------------------------------------------

=========================================================================
Timing constraint: NET "CTLR/SCLK" PERIOD = 45.000000 nS ;
    1054 items analyzed, 0 timing errors detected.
    Minimum period is  30.140ns.
   -------------------------------------------------------------------------
   Slack:     7.430ns path CTLR/VID/S2 to ME_WE_O- relative to
             22.500ns delay constraint (two-phase clock)

Path CTLR/VID/S2 to ME_WE_O- contains 3 levels of logic:
   Path starting from Comp: CLB_R7C18.K (from CTLR/SCLK)
   To                   Delay type         Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  --------
   CLB_R7C18.YQ         Tcko                  1.830R  CTLR/VID/S2
                                                      CTLR/VID/V_SM/S2/$1I1
   CLB_R2C30.F2         net (fanout=11)       6.631R  CTLR/VID/S2
   CLB_R2C30.X          Tilo                  1.700R  CTLR/VID/V_FGEN/WE
                                                      CTLR/VID/V_FGEN/M1/$1I5
   P148.O               net (fanout=1)        4.420R  CTLR/VID/V_FGEN/WE
   P148.OK              Took                  0.489R  ME_WE_O-
                                                      CTLR/VID/V_FGEN/ME_WE
   -------------------------------------------------
   Total (4.019ns logic, 11.051ns route)     15.070ns (to CTLR/SCLK)
         (26.7% logic, 73.3%% route)

-------------------------------------------------------------------------
Slack:     8.037ns path CTLR/VID/S2 to TR_OE_O- relative to
             22.500ns delay constraint (two-phase clock)

Path CTLR/VID/S2 to TR_OE_O- contains 3 levels of logic:
   Path starting from Comp: CLB_R7C18.K (from CTLR/SCLK)
   To                   Delay type         Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  --------
   CLB_R7C18.YQ         Tcko                  1.830R  CTLR/VID/S2
                                                      CTLR/VID/V_SM/S2/$1I1
   CLB_R2C30.G1         net (fanout=11)       6.458R  CTLR/VID/S2
   CLB_R2C30.Y          Tilo                  1.760R  CTLR/VID/V_FGEN/WE
                                                      CTLR/VID/V_FGEN/M2/$1I5
   P150.O               net (fanout=1)        3.926R  CTLR/VID/V_FGEN/OE
   P150.OK              Took                  0.489R  TR_OE_O-
                                                      CTLR/VID/V_FGEN/TR_OE
   -------------------------------------------------
   Total (4.079ns logic, 10.384ns route)     14.463ns (to CTLR/SCLK)
         (28.2% logic, 71.8%% route)

-------------------------------------------------------------------------

All constraints were met.

Timing summary:
   ---------------

Timing errors: 0  Score: 0

Constraints cover 1459 paths, 0 nets, and 631 connections (75.5% coverage)

Design statistics:
      Minimum period:  32.913ns (Maximum frequency:  30.383MHz)

Analysis completed Tue Apr 28 13:55:21 1998
   -------------------------------------------------------------------------