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IBUF_selectIO

Single Input Buffer with Selectable I/O Interface

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Primitive

figures/x3830n.gif

For Virtex, IBUF and its variants (listed below) are single input buffers whose I/O interface corresponds to a specific I/O standard. The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. For example, IBUF_SSTL3_II is a single input buffer that uses the SSTL3_II I/O-signaling standard.

An IBUF isolates the internal circuit from the signals coming into a chip. IBUFs are contained in input/output blocks (IOBs). IBUF inputs (I) are connected to an IPAD or an IOPAD. IBUF outputs (O) are connected to the internal circuit.

The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectI/O buffer components. Refer to the “SelectI/O Usage Rules” section below for information on using these components.

Component
I/O Standard
VREF
IBUF
LVTTL
N/A
IBUF_LVCMOS2
LVCMOS2
N/A
IBUF_PCI33_3
PCI33_3
N/A
IBUF_PCI33_5
PCI33_5
N/A
IBUF_PCI66_3
PCI66_3
N/A
IBUF_GTL
GTL
0.80
IBUF_GTLP
GTL+
1.00
IBUF_HSTL_I
HSTL_I
0.75
IBUF_HSTL_III
HSTL_III
0.90
IBUF_HSTL_IV
HSTL_IV
0.75
IBUF_SSTL2_I
SSTL2_I
1.10
IBUF_SSTL2_II
SSTL2_II
1.10
IBUF_SSTL3_I
SSTL3_I
0.90
IBUF_SSTL3_II
SSTL3_II
1.50
IBUF_CTT
CTT
1.50
IBUF_AGP
AGP
1.32

SelectI/O Usage Rules

The Virtex architecture includes a versatile SelectI/O interface to multiple voltage and drive standards. To select an I/O standard, you must choose the appropriate component from the Virtex library. Each standard has a full set of I/O buffer components (input, in/out, output, 3-state output). For example, for an input buffer of the GTL standard, you would choose IBUF_GTL. Refer to the “IBUF_selectIO”, “IBUFG_selectIO”, “IOBUF_selectIO”, “OBUF_selectIO”, and “OBUFT_selectIO” sections for information on the various input/output buffer components available to implement the desired standard.

The hardware implementation of the various I/O standards requires that certain usage rules be followed. As shown in the following table, each I/O standard has voltage source requirements for input reference (VREF), output drive (VCCO), or both. Each Virtex device has eight banks (two on each edge). Each bank has voltage sources shared by all I/O in the bank. Therefore, in a particular bank, the voltage source (for either input or output) must be of the same type. The Input Banking (VREF) Rules section and the Output Banking (VCCO) Rules section below summarize the SelectI/O component usage rules based on the hardware implementation.

I/O Standard
VCCO
VREF
LVTTL
3.3
N/A
LVCMOS2
2.5
N/A
PCI33_3 (PCI 33MHz 3.3V)
3.3
N/A
PCI33_5 (PCI 33MHZ 5.0V)
3.3
N/A
PCI66_3 (PCI 66MHz 3.3V)
3.3
N/A
GTL
N/A
0.80
GTL+
N/A
1.00
HSTL_I
1.5
0.75
HSTL_III
1.5
0.90
HSTL_IV
1.5
0.75
SSTL2_I
2.5
1.10
SSTL2_II
2.5
1.10
SSTL3_I
3.3
0.90
SSTL3_II
3.3
1.50
CTT
3.3
1.50
AGP
3.3
1.32

Input Banking (VREF) Rules

The low-voltage I/O standards that have a differential amplifier input require a voltage reference input (VREF). The VREF voltage source is provided as an external signal to the chip that is banked internal to the chip.

Output Banking (VCCO) Rules

Because Virtex has multiple low-voltage standards and also needs to be 5V tolerant, some control is required over the distribution of VCCO, the drive source voltage for output pins. To provide for maximum flexibility, the output pins are banked. In comparison to the VREF sources described above, the VCCO voltage sources are dedicated pins on the device and do not consume valuable IOBs.

Banking Rules for OBUFT_selectIO with KEEPER

If a KEEPER symbol is attached to an OBUFT_selectIO component (3-state output buffer) for an I/O standard that requires a VREF (for example, OBUFT_GTL, OBUFT_SSTL3_I), then the OBUFT_selectIO component follows the same rules as an IOBUF_selectIO component for the same standard. It must follow both the input banking and output banking rules. The KEEPER element requires that the VREF be properly driven.

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