| Element | XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|---|
| OFDX | N/A | Primitive | Primitive | N/A | N/A | Primitive | Primitive | Macro |
| OFDX4, OFDX8, OFDX16 | N/A | Macro | Macro | N/A | N/A | Macro | Macro | Macro |
OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops. The flip-flops are located in an input/output block (IOB) for XC4000E. The Q outputs are connected to OPADs or IOPADs. The data on the D inputs is loaded into the flip-flops during the Low-to-High clock (C) transition and appears on the Q outputs. When CE is Low, flip-flop outputs do not change.
The flip-flops are asynchronously cleared with Low outputs, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.
| Inputs | Outputs | ||
|---|---|---|---|
| CE | D | C | Q |
| 1 | D |  | dn |
| 0 | X | X | No Chg |
| dn = state of referenced input one setup time prior to active clock transition | |||
Figure 8.40 OFDX Implementation Virtex |  |
Figure 8.41 OFDX8 Implementation XC4000, Spartans, Virtex | |
