Controlling Timing Paths

There are two mechanisms that can improve the timing of your design:

• Global Timing Optimization
  
  
• Timing Constraints
  
  

Optimization for Speed

By default, the fitter performs timing optimization on logic paths in your design. Timing optimization will automatically shorten your logic paths as much as it can. In general, timing optimization optimizes logic and allocates the fastest available resources for the longest paths in your design, assuming all paths are equally critical. In some cases, the fitter trades off density for a speed advantage.

These default fitter option settings that favor optimization for speed are included in a template named Optimize Speed. Timing Optimization will be set ON for all CPLD families, and Use Local Macrocell Feedback and Use Local I/O Pin Feedback will be set to on for XC9500 devices. If you want to change to a template containing fitter options that favor optimization for density, select the Optimize Density template:

1. Design Implement
   
   
2. Press the Options softkey.
   
   
3. Adjacent to the Edit Template button, click once on the down arrow and select the Optimize Density implementation option. If you revert to optimizing for timing, set the template for default or Optimize Speed.
   
   

To turn off timing optimization from Unix, specify the "-notiming" parameter on the cpld command line as follows:

cpld -notiming design_name

Disabling timing optimization will optimize for density and may significantly reduce the processing time of the CPLD fitter.

Timing Constraints

The Synopsys Design Compiler (or FPGA Compiler) provides a set of timing constraint commands that you can use to specify the timing requirements of your Xilinx design. After compiling your design, the Xilinx software reads both your design netlist and your dc_shell timing constraint commands and performs timing optimization according to your specifications. You can enter timing constraints in the Design Analyzer, the dc_shell command line, or a dc_shell script file. The Synopsys Compiler does not use your timing constraints to optimize your logic or infer library cells during compilation of a CPLD design. All timing optimization is performed by the CPLD fitter after reading your dc_shell timing specifications.

The following path types can be controlled using timing constraints:

This section lists the Synopsys commands that you can use to create timing specifications for your Xilinx CPLD designs.

Clock Period

You can use the dc_shell command create_clock to declare a clock input port and place a period timing specification on the specified clock net. The register-to-register delays between all flip-flops on the named clock will be constrained by the specified period.

The create_clock command creates a cycle time specification on the specified clock signal as follows:

create_clock clock_port -period delay

where clock_port is the name of the clock input port and delay is the clock cycle time in nanoseconds.

NOTE

The Synopsys max_period command is not supported by the Xilinx fitter; use the create_clock command instead.

Point-to-Point Delays

The dc_shell command set_max_delay specifies delay constraints for specific paths originating from input (or I/O) ports or flip-flop cells and terminating at output (or I/O) ports or flip-flop cells. The syntax of the set_max_delay command is:

set_max_delay delay -from source -to destination

For example, to specify the propagation delay from the CLEAR input port to the DONE output port:

set_max_delay 20 -from CLEAR -to DONE

The following table describes the various source and destination combinations you can use with the set_max_delay command.

Table 2_1 set_max_delay

Note 1. To specify input setup time with respect to a clock pad, refer to the Input Port Timing Constraint section below.

Note 2. To specify clock-to-output delays beginning at the clock input pad, either use the set_max_delay command specifying the clock port as the source, or refer to the Output Port Timing Constraint section below.

If you use the set_max_delay command to specify a register setup time constraint on an input port to a named register, then the delay you specify in the command must be larger than the actual setup time requirement you want to have between the data and clock pads of the device. The amount you will need to add to your desired pin-to-pin setup time is the delay of the clock path from clock pad to the flip-flop.

To use the following command form to specify setup time:

set_max_delay delay -from input_port -to register

you should specify your delay value according to the following relationship:

delay = tSU + tGCK

where:

delay is the delay value specified in the set_max_delay command,

tSU is the desired setup time requirement on the data input pad with respect to the clock input pad, and

tGCK is the delay of the clock path from clock pad to the flip-flop's clock pin.

For XC9500 devices, the tGCK delay parameter is listed in the device data sheets.

Similarly, if you use the set_max_delay command to specify clock-to-output delay from a named register to an output port, the delay you specify in the command must be smaller than the actual pad-to-pad delay you want to have on the device. The amount you will need to deduct from your desired pin-to-pin delay is the delay of the clock path from clock pad to the flip-flop.

To use the following command form to specify clock-to-output delay:

set_max_delay delay -from register -to output_port

you should specify your delay value according to the following relationship:

delay = tCO - tGCK

where:

delay is the delay value specified in the set_max_delay command,

tCO is the desired clock-to-output delay between the clock input pad and the output pad, and

tGCK is the delay of the clock path from clock pad to the flip-flop's clock pin.

Output Port Timing Constraint

The set_output_delay command establishes clock-to-output delay specifications based on values specified in the create_clock or set_max_delay constraints or creates tighter constraints for named output ports as follows:

set_output_delay delay -clock clock output_port

When the named output ports are driven by registers covered by a create_clock period constraint, the set_output_delay constraint specifies how much time (delay) before the next clock edge the named outputs need to become stable.

In this case, the set_output_delay constraint specifies the delay path between the clock input pin of the CPLD device and the named output pin(s) according to the following relationship:

set_output_delay_value = create_clock_period_value - cpld_clock_to_output_delay

where set_output_delay_value is the delay value specified in the set_output_delay constraint, create_clock_period_value is the period value specified in a previous create_clock constraint, and cpld_clock_to_output_delay is the desired worst-case propagation delay between the clock input pin and output pin(s) of the CPLD.

For example, the following pair of commands sets the register-to-register delays between all flip-flops clocked by C1 to 20 ns and sets the clock-to-output delay from C1 to output Q2 to 6 ns:

create_clock C1 -period 20

set_output_delay 14 -clock C1 Q2

This command also changes the values of pad-to-pad or clock-to-output delay specifications created by the set_max_delay command, by making the constraints tighter by the amount specified by the delay value for the named outputs.

When using the set_output_delay constraint, the named clock must be explicitly declared as a global clock input port by using the dc_shell command

set_pad_type -exact BUFG clock

as described in the section Special I/O Ports earlier in this chapter.

Input Port Timing Constraint

The set_input_delay command establishes register setup time specifications based on create_clock or set_max_delay commands or creates tighter constraints on named input ports as follows:

set_input_delay delay -clock clock input_port

When the named input ports feed into registers covered by a create_clock period constraint, the set_input_delay constraint specifies how much time (delay) after the previous clock edge the named inputs are expected to become stable.

In this case, the set_input_delay constraint specifies the setup time requirements between data input pin(s) and the clock input pin of the CPLD device according to the following relationship:

set_input_delay_value = create_clock_period_value - cpld_external_setup_time

where set_input_delay_value is the delay value specified in the set_input_delay constraint, create_clock_period_value is the period value specified in a previous create_clock constraint, and cpld_external_setup_time is the desired worst case setup time between the data input pin(s) and the clock input pin of the CPLD.

For example, the following pair of commands sets the register-to-register delays between all flip-flops clocked by C1 to 20 ns and sets the setup time requirements on input D2 with respect to the C1 device input pin to 8 ns:

create_clock C1 -period 20

set_input_delay 12 -clock C1 D2

This command also changes the values of pad-to-pad delay or register setup time specifications created by the set_max_delay command, by making the constraints tighter by the amount specified by the delay value for the named inputs.

When using the set_input_delay constraint, the named clock must be explicitly declared as a global clock input port by using the dc_shell command

set_pad_type -exact BUFG clock

as described in the section Special I/O Ports earlier in this chapter.

NOTE

The dc_shell command set_false_path is not supported for CPLD designs at this time.

You can also enter timing constraints interactively using the Constraint Editor tool invoked from the Design Manager.

Disabling Timing Specifications

If you used timing constraints when compiling your design but want to run the fitter without using your timing specifications, you can temporarily ignore all timing specifications by removing the check from the Use Timing Constraints option in the Implementation Options template.

1. Design Implement
   
   
2. Press the Options softkey.
   
   
3. Select Edit Template
   
   
4. Select the Basic tab.
   
   
5. Remove the check mark next to Use Timing Constraints.
   
   

If you want to do this on the Unix command line, use the -ignorets parameter with the CPLD command as follows:

CPLD -ignorets design_name

Reducing Levels of Logic

The XC9500 architecture, like most CPLD devices, is organized as a large, variable-sized combinational logic resource (the AND-array and XOR gate) followed by a register. If you place combinational logic before a register in your design, the fitter maps the logic and register into the same macrocell. The output of the register is then directly available at an output pin of the device. If, however, you place logic between the output of a register and the device output pin, a separate macrocell must used to perform the logic, decreasing both the speed and density of your design. The following example shows two functionally similar styles for designing a selectable divide-by-2 or divide-by-4 counter. The first design style is inefficient for CPLD architectures; the second example is more efficient.

-- Inefficient style for CPLDs: 
   process (CLOCK) 
     begin 
     if (CLOCK'event and CLOCK='1') then 
       DIV2 <= not DIV2; 
       DIV4 <= DIV4 xor DIV2; 
     end if; 
   end process; 
   DIV_OUT <= DIV2 when (SEL4='0') else DIV4;

-- More efficient style for CPLDs: 
   process (CLOCK) 
     begin 
     if (CLOCK'event and CLOCK='1') then 
       DIV2 <= not DIV2; 
       if (SEL4='1') then 
           DIV_OUT <= (DIV_OUT xor DIV2); 
        else 
           DIV_OUT <= not DIV_OUT; 
        end if;                     >
     end if; 
   end process;