XC9500 family devices (except XC9536) contain high-speed local feedback paths interconnecting the macrocells within each function block. Local feedback paths bypass the FastCONNECT array and provide shorter propagation delays between macrocells. Using local feedback requires that all logic sourcing and receiving local feedback signals be mapped to the same function block locations within the target device. When a timing constraint is applied to a path which would require local feedback routing in order to meet the specified constraint, the fitter will attempt to map the logic spanned by the timespec into the same function block and use local feedback routing.
If the fitter does not find a way to map logic into the same function block, you can explicitly map your logic to allow the fitter to use local feedback routing. To explicitly map a logic node to a specific function block, apply the LOC attribute to the signal (net) or cell as follows:
set_attribute signal_name loc FBnn -type string
where nn is a legal function block number for the target device.
This option, when enabled, will use local feedback routing whenever a feedback node connects between macrocells that happen to get mapped to the same function block. This is done in addition to using local feedback to satisfy timespecs. The software will create clusters of equations and attempt to place them in the same function block. However, the software is allowed to break a cluster if it is impossible to place it in one function block.
Local Macrocell Feedback optimization can be selected from the Advanced tab of the Implementation Options template of the Design Manager as follows:
ImplementTo specify local feedback using the cpld command, use the command option -localfbk
cpld -localfbk design_name
This option enables the software to use local I/O pin feedback whenever possible in an XC9500 design (except XC9536). Pin feedback takes less time than the XC9500 FastCONNECT path. The software uses the pin feedback path instead of the FastCONNECT path for output pin signals that do not have tristate control or slow slew rate. By default, this option is off.
Local Pin Feedback optimization can be selected from the Advanced tab of the Implementation Options template of the Design Manager as follows:
ImplementTo specify pin feedback from the cpld command use the command option -pinfbk.
cpld -pinfbk design_name
