The Synopsys interface supports both VHDL and Verilog HDL design synthesis. Either the Synopsys FPGA Compiler or Design Compiler can be used to compile CPLD designs; there are no differences between the two compilers with regard to the supported features or implementation efficiency. In the following discussion, the term "compiler" refers to either FPGA Compiler or Design Compiler.
This chapter describes how to compile your design using the Synopsys Design Compiler shell (dc_shell). You can also use the Synopsys graphical user interface, Design Analyzer, to process your designs. This chapter also describes how to implement your design using both the Xilinx Design Manager and the cpld command-line. It contains the following sections:
Before compiling you will need to develop your VHDL or Verilog HDL source file (design_name.vhd or design_name.v). Usually it is a good idea to perform a functional simulation of your source design using VSS or some VHDL or Verilog compatible simulator before trying to synthesize it. See the "Simulating Your Design" chapter for information on functional simulation using VSS.
