As a first step in the functional simulation process, create the simulation network (VSM file) and load it into ViewSim to simulate the design. The procedure for preparing for functional simulation on a Xilinx design depends on which components you use to enter the design.
This section describes these two categories of designs.
This category includes designs that contain modules with non-schematic models (such as ABEL modules) and components with parameterized functionality (for example, the behavior of a ROM component depends on the assigned INIT attribute).
A complete list of such modules follows.
This category includes all designs not included in Category A. Category B designs do not contain any non-schematic modules or parameterized components. The presence of LogiBLOX modules does not exclude a design from this category, except for RAM modules.
In order to functionally simulate a design that contains modules with non-schematic models and components with parameterized functionality, compile the design to a single netlist file (NGD). You must run two programs to compile the design to this netlist, then run two to bring the design back into the Viewlogic environment for the simulation.
Part of the installation and setup process includes running the Custmenu command. This command sets up five menu choices within ViewDraw, including one entitled “Xilinx Functional Simulation.” With the top-level schematic open in ViewDraw, select this menu item. When the GUI opens, select the family for this design and click on OK.
The Functional Simulation GUI runs five programs.
The “Using Powerview to Create the Functional Simulation Netlist for Category A Designs” section details the specific command lines that run within the Functional Simulation GUI.
The Functional Simulation GUI produces a func_sim.vsm file. The name of this file differs from the name of the original schematic, so you need to tell Viewsim which schematic to annotate. See the “Annotating Values to Original Schematic” section for details.
After creating the VSM file you can move on to the “Loading the Design into the Viewlogic Simulator” section.
To create a VSM file for Category A designs, first write out an EDIF netlist from Powerview using either the “netlist out” button in the Powerview Cockpit or from a UNIX prompt. The EDIFNETO tool translates a Viewlogic design into an EDIF 2.0.0 netlist.
Double-click on the “netlist out” button from the Powerview Cockpit, then fill out the following two fields.
Click on OK or Apply to write the design.edn file.
This command line syntax follows.
edifneto -l xilinx design
Use the name of the top-level design for the design parameter.
Next, compile the design to one complete and flattened NGD file. The syntax for NGDBUILD follows.
ngdbuild -p part design.edn
This Xilinx program reads the EDIF netlist, expands any LogiBLOX modules, and generates gate models for non-schematic modules. It produces a design.ngd file.
Use the -p option only if there a part type is not specified in the schematic. You need specify only the architecture family if you do not yet know the exact device and package information. For example, you can specify “xc4000x” rather than “XC4028XPG299-3.”
After creating an NGD file to represent your entire flattened design, you must create a new EDIF file to send back to the Viewlogic tools for the functional simulation. Use NGD2EDIF with the following syntax.
ngd2edif -v viewlog design.ngd func_sim.edn
This Xilinx program generates a gate-level EDIF netlist for the complete expanded design. All design logic is expressed in terms of the Xilinx simprims library components.
The -v option tells NGD2EDIF to perform some Viewlogic-specific processing when generating the EDIF netlist.
The EDIF file is named func_sim.edn, not the original design name to avoid overwriting the original EDIF netlist and the original WIR file(s) in the next step. The name “func_sim.edn” is not required, but it should be a name different from the design name.
If the design contains RAM elements, and if the target family supports initial values on RAM, NGD2EDIF also generates a func_sim.xmm file. This file contains ViewSim LOADM commands to model the initial contents, discussed in the “Loading XMM Files” section.
Read this new EDIF file back into the Powerview environment. Double-click on the “netlist in” button from the Powerview Cockpit.
Fill in the “EDIF netlist file” field if the EDIF file is located in the project directory. Otherwise, ensure the “Pathname for output files” field points to the project directory.
Click on OK or Apply to read in the func_sim.edn file.
This command line syntax follows.
edifneti func_sim.edn
EDIFNETI reads the EDIF netlist generated by NGD2EDIF and produces WIR files to represent the design. Because the EDIF netlist is hierarchical, EDIFNETI generates one WIR file for each level of hierarchy. Lower-level WIR files are named xba1.1, xba2.1 and so on, to avoid conflicts with the original design WIR files.
Next, in the Powerview Cockpit, double-click the VSM icon. This opens the ViewSim Wirelister. Follow the following steps to create a functional simulation netlist from the func_sim.edn file.
Do not select the design.1 or design.edn file as the input, as this uses the uncompiled schematic design instead of the compiled version that you just created.
This Viewlogic program reads the WIR files generated by EDIFNETI and produces a single VSM file, for use by Viewsim.
Enter the following on a UNIX command line to run this command.
vsm func_sim
Preparing a Category B design for functional simulation requires running the VIEWlogic VSM program. You call this program from ViewDraw or from the Workview Office Toolbar. How you do this depends on whether or not LogiBLOX modules were used, and what type of models it created.
In ViewDraw, select Tools 
Create Digital Netlist, or from the Workview Office Toolbar, select the VSM icon, shown in the following figure.
This opens the ViewSim Wirelister. Follow the following steps to create a functional simulation netlist from your schematic.
At this point, the ViewSim Wirelister appears similar to the following figure.
Figure 4.1 Completed ViewSim Wirelister for Category B |  |
If the design contains no LogiBLOX modules, or if LogiBLOX created EDIF models for its modules, click OK to start the ViewSim Wirelisting flow.
If LogiBLOX created VHDL models for its modules, you need to fill in one more field. Under the Advanced tab, fill in the Wirelist Design to Level field with “vhdl,” as shown in the next figure.
Figure 4.2 Advanced Tab for VHDL Models | |
The vhdl argument tells VSM to netlist down to LogiBLOX modules. The actual VHDL modules will be incorporated by the simulator.
