This section contains information for controlling the FPGA/CPLD layout from the schematic in assigning pin locations, designing FAST pads, using the I/O flip-flops, and saving the Calc schematic.
Let the automatic placement and routing program, PAR, define the pinout. Pre-assigning locations to the I/Os can sometimes degrade the performance of the place and route tools. However, at some point you must lock the pinout of a design so that it can integrate into a board design. Define the initial pinout by running the place and route tools without pin assignments, then locking down the I/O placement so that it reflects the locations chosen by the tools. Assign pin locations to I/O in the tutorial schematics so that the Calc design can function in the Xilinx demonstration boards. Because the design is fairly simple, these pin assignments do not adversely affect the ability of PAR to place and route the design completely.
Specify pin locations by attaching a LOC property to a pad component. Modify the LOC property on the pad associated with the STACKLED0 signal on the Calc schematic as follows.
Figure 8.36 Assigning a Location to an Output Net |  |
For simplicity, the other pin locations for the Calc design reside in a data file known as a constraint file, described in a later section. You can leave the other location values undefined. Valid pin locations vary depending on the package. PLCC, HQFP, and other “numeric-only” package pins receive the designation “P” followed by the pin number, such as P17. PGA and other grid-array package pins use alphanumerics such as A12. The Programmable Logic Data Book lists the pinouts of each FPGA and CPLD for each package that Xilinx supplies.
Modify output slew rate by assigning a FAST attribute to the output buffer, as shown in the “Designating a FAST Pad” figure. The default slew rate is SLOW. “Fast” pads have different timing specifications and draw more current than “slow” (slew-rate-limited) pads. See The Programmable Logic Data Book for timing specifications for the various slew rate modes.
Add a FAST attribute to the led output display drivers attached to the STACK[3:0] bus as follows.
Figure 8.37 Designating a FAST Pad | |
Figure 8.38 Pad Location and FAST Attribute on STACKLED0 | |
Xilinx XC3000A and XC4000E/EX devices use two flip-flops in each Input Output Block (IOB). Each pad has an associated input flip-flop and output flip-flop. You can also configure input flip-flops as latches and output flip-flops as 3-state. You access these elements using the library components IFD, ILD, OFD, and OFDT, as well as other higher-level macros that contain these components. For more information on these library elements, consult the Libraries Guide.
IOB flip-flops, whenever possible, free up internal CLB resources. IOB flip-flops register the switch inputs. As shown in the “SWITCH7 Schematic Using Input Flip-Flops” figure, the SWITCH7 macro attached to the input bus SW[7:0] in the lower-left area of the schematic has an underlying schematic that consists of seven IFD (input flip-flip D-type) Xilinx primitives. Using similar flip-flops, such as FDs, wastes the flip-flops in the IOB, leaving valuable CLB resources occupied.
Figure 8.39 SWITCH7 Schematic Using Input Flip-Flops | |
Before continuing, check and save the changes made to Calc, as shown earlier in this tutorial.
