To complete the tutorial design, you need to add a few design objects to the Calc schematic using ViewDraw.
If you must stop the tutorial at any time, save your work by selecting File 
Save and Check from the menu bar. The results of the Check portion appear at the bottom of the ViewDraw window. You can also check all the schematic sheets in the design by selecting Tools Check Project.
You do not create the top-level schematic of the Calc tutorial design; it already exists. Each of the blocks in the schematic, such as CONTROL or ALU, links to a second-level module that describes its logic. Additionally, any second-level module can contain another block that references a third-level drawing, and so on. This organization is known as a hierarchical structure.
In this tutorial, you add three symbols to the ALU block schematic to complete it. First, you create the ANDBLK2 and ORBLK2 symbols and their underlying schematics and then add them to the schematic. Additionally, you add the FD4RE symbol from the Unified Libraries to the ALU block. After finishing the ALU block, you add the STARTUP block to the top-level Calc schematic to tie the device's global reset network to a device pin.
The Calc design is a four-bit processor with a stack. The processor performs functions between an internal register and either the top of the stack or data input from external switches. The register stores the results of the various operations and displays them in hexadecimal on a seven-segment display. The top value in the stack displays in binary on a bar LED. A count of the items in the stack displays as a “gauge” on another bar LED.
The design consists of the following functional blocks
Before proceeding, close (quit) the Calc schematic window. If a dialog box appears asking if you want to save any changes, choose NO.
Open. Set the directory to Primary and the Type to Symbol. Box from the pulldown menu. Pin. Undo to undo the last command. If you make a mistake after placing a pin, first undo the Add Pin feature by selecting the icon in the Object Toolbar that looks like the mouse cursor. Select the pin with a left mouse click and delete it by selecting Edit Delete. You can also click and drag to reposition it.Figure 8.13 Adding Pin Label Information for A[3:0] |  |
Figure 8.14 Adding Pin Attribute Information for Q[3:0] | |
Figure 8.15 ANDBLK2 Symbol with Pins and Labels Added | |
You can add comment text to a symbol to make it more easily identifiable on a schematic, or to annotate it without modifying its function. To add text to the symbol, perform the following steps.
Text.To modify the text after it has been placed, select the cursor icon and double click on the text. This brings up the text properties box, where you can modify the size, color, font, and orientation of the text, as well as edit the text itself. You can use this method to modify any text on the symbol, such as pin names.
You use labels and text for completely different purposes. Labels differentiate nets, buses, pins and components, passing these strings on into the Edif netlist and beyond. Text annotates symbols and schematics with information for documentation purposes. Text does not pass onto any netlists beyond the wire files.
Figure 8.16 Completed ANDBLK2 Symbol | |
To save the ANDBLK2 symbol, perform the following steps.
Save.Figure 8.17 Output from Check | |
Create the symbol for ORBLK2, as shown in the “Completed ORBLK2 Symbol” figure. Because ORBLK2 is similar to ANDBLK2, use the ANDBLK2 symbol and modify the text.
Figure 8.18 Completed ORBLK2 Symbol | |
Save Copy As.
WARNINGYou must select the Save Copy As command instead of Save to prevent overwriting the original ANDBLK2 symbol file.
So far, you created symbols for ANDBLK2 and ORBLK2. The next step involves creating schematics for these blocks. You can then reference the schematics in a higher-level schematic by placing the symbols.
Open. A dialog box appears. Component. Use the Unified Libraries for new designs. All design elements should come from the Xilinx Unified Library, LogiBLOX, or a user-created library; do not place any component from the Builtin, Xbuiltin, or Simprims libraries on your schematics. Also, the Add Component command does not place LogiBLOX components directly on the schematic. See the “Using LogiBLOX” section of this tutorial for more information.
Figure 8.19 Placing a Component | |
After placing the AND2, notice that the symbol for the AND2 still appears in the Add Component box. To place more components, simply repeat the click and move process to place more components of any type onto your schematic. When completed, use the Close button to close the Add Component box.
You can also use the Copy command to add more components by copying a component that already appears on the schematic.
Copy. Paste. Component command) until you have a total of four AND2s. Use the View pulldown to change the size and location of the working window. Note the function hot keys for these commands.If you make a mistake when placing a component, you can easily move the component.
Press F4 to view the entire schematic. The schematic now looks like the next illustration.
Figure 8.20 Component Placements for ANDBLK2 | |
You can draw a set of signals as a bus rather than as several separate wires. You do not have to physically connect a bus to the nets that make up the bus. Several schematics in the Calc design have short bus segments that connect to nothing, so that a bus pin can represent the bus on the symbol. A bus must exist on the schematic if you use a bus pin is for a set of signals.
Add buses to the schematic as follows.
Bus. Note the now-depressed Bus icon on the Object Toolbar. Pressing this button returns you to “Add Bus” mode. Delete to remove the bus segments.Figure 8.21 ANDBLK2 Schematic with Buses | |
Add nets to attach the appropriate pins on the gates to the buses. You can enlarge the view of the schematic to make it easier to draw the nets.
Net. Note the now-depressed Net icon on the Object Toolbar. Pressing this button returns you to “Add Net” mode.Figure 8.22 Connecting a Net | |
You need only this physical connection to logically connect a net to a bus. Bus rippers are not supported. However, the name of the net must have the same root name of the bus plus an index. For example, with a bus named A[3:0], you must label the net that is bit zero of bus A A0. You need no parentheses for the net name.
Add the remaining nets and labels to the schematic as shown in the following figure.
Figure 8.23 Completed ANDBLK2 Schematic | |
To add a label to a bus or net, simply double-click on that net or bus. In the Net Properties box that pops up, add the name in the Label field. For buses, include the bounds using square brackets, as shown in the “Net Properties Dialog Box” figure.
You can also change the size of the text in this dialog box by changing the number in the Size field. All of the existing labels in this tutorial are 14 point. You can also change the default text size by choosing Project Settings and changing the Size under the Text tab. Click OK.
Figure 8.24 Net Properties Dialog Box | |
If you accidently select any elements besides the net or bus you want to label, press F2 and repeat the selection procedure.
To reposition a label, single-click on the label so that the net or bus is deselected. Click and drag the label to the final position.
You make the logical connection between the symbol and its underlying schematic simply by name. You find the name of each pin on the symbol in its corresponding schematic; no special connecting components are required. Naming the buses A[3:0], B[3:0] and Q[3:0] achieved the connectivity between the schematic and symbol. The Check program produces an error if a symbol pin is not represented on the underlying schematic.
The schematic is now complete. Check and save the schematic by selecting File Save and Check. If no dialog box pops up, you see the following message at the bottom of the screen.
Check complete. 0 errors and 0 warnings in project ANDBLK2
If you do not see this message, check the errors in the dialog box and correct them before saving again.
The ORBLK2 schematic is similar to the ANDBLK2 schematic. To create schematics for the ORBLK2 symbol, you can use the ANDBLK2 schematic and replace the four AND2 gates with four OR2 gates.
Figure 8.25 Selecting Gates | |
Replace to bring up the Find dialog boxFigure 8.26 Completed ORBLK2 Schematic | |
Save Copy As. A dialog box appears.WARNINGYou must select the Save Copy As command instead of Save to prevent overwriting the original ANDBLK2 schematic file.
So far, you created symbols for ANDBLK2 and ORBLK2, and the underlying schematics for these symbols. Next, place the symbols in the ALU block schematic.
Open.All additions you need to make reside in the ALU schematic; click the right mouse button and select Schematic. This pushes into the schematic below the ALU symbol.
To navigate through the hierarchy, you can use a right mouse button click to select a lower level symbol or schematic if the component is selected, or another sheet of the same schematic if you selected no symbol. Buttons also exist for these commands on the View Toolbar.
You can now place the ANDBLK2 and ORBLK2 symbols on the schematic, as shown in the “Adding ANDBLK2 and ORBLK2 to ALU Schematic” figure. You can place the symbols using the same procedure you used to place the AND2 gate from the Xilinx libraries when you created the ANDBLK2 schematic.
Component. A dialog box appears.Take all user-defined blocks that you add to your design from the Primary directory (or other user-created library directories), not the discrete path that describes the project directory. This ensures adding the proper aliases to the instantiated components and avoids problems further along in your flow.
Figure 8.27 Adding ANDBLK2 and ORBLK2 to ALU Schematic | |
Undo to step back.Add the FD4RE and AND5B2 components to the ALU schematic. Both of these components reside in the Xilinx Unified Libraries. The FD4RE component consists of four flip-flops with clock enables. The AND5B2 component is a five-input AND gate with two inputs inverted (“bubbled,” hence the “B”).
These components reside in all libraries, including those for the XC4000E and XC9500.
Component from the menu bar. Figure 8.28 Adding FD4RE and AND5B2 to ALU Schematic | |
This section includes information on adding nets, buses, and labels to the FD4CE and AND5B2 symbols, and on completing the addition of ANDBLK2 and ORBLK2 to the ALU schematic.
Complete the addition of the FD4RE and AND5B2 symbols by adding nets, buses, and labels as follows.
Label field and add any attributes under the Attributes tab. The nets appear as shown in this figure.Figure 8.29 Nets, Buses and Labels for FD4RE and AND5B2 | |
Next, complete the addition of ANDBLK2 and ORBLK2 to the ALU schematic.
Add labels to components. Error and warning messages often reference component labels, and labels also appear in simulation netlists. References to net names at lower levels of hierarchy use the following format.
...component_label\component_label\net_label
In the ALU schematic, labels already exist for the MUXBLK2, XORBLK2, and MUXBLK5 blocks.
To add a label to the ORBLK2 placement, follow these steps.
Figure 8.30 Adding Component Labels to ALU Schematic | |
The completed ALU schematic appears in the following figure.
Figure 8.31 Completed ALU Schematic | |
Check and save the schematic. If errors occur, resolve them and then check and save the schematic again.
The Xilinx libraries contain three types of elements.
You place all three types of library elements on a schematic in exactly the same way.
Soft macro schematics resemble the schematics you create for your own designs. In fact, you can load one of these schematics and use the File Save Copy As command to save it under another name. You can then edit this new schematic to customize it to your needs.
Open the schematic underneath the FD4RE symbol as follows.
Figure 8.32 FD4RE Schematic from XC4000E Library | |
The following description of RPMs contains detailed information on the XC4000E architecture. Refer to The Programmable Logic Data Book for more information about the XC4000E CLB structure and fast carry logic.
If your design does not target the XC4000E family, read this section, but do not perform any of the commands. Continue the tutorial with the “Completing the Calc Design” section.
The ALU contains a component from the Xilinx library, ADSU4, a four-bit wide adder/subtracter. If your design targets the XC4000E library, this schematic implements as a Relationally Placed Macro (RPM). If your design does not target the XC4000E library, ADSU4 implements without this placement information.
RPM schematics resemble schematics you create for your own designs. In fact, you can load one of these schematics and use the File Save Copy As command to save it under another name. You can then edit this new schematic to customize it to your needs.
Elements placed in the ADSU4 RPM schematic include CY4 components and FMAPs. The CY4 symbol gives you the ability to specify fast carry logic functionality from the schematic. Fast carry logic, a hardware feature in XC4000E parts, allows very fast arithmetic-type functions.
The FMAPs map logic functions to function generators in Configurable Logic Blocks (CLBs), arranged in a rectangular grid in the die. Both CY4 symbols and FMAP symbols have RLOC attributes. RLOCs attach to the symbols that assign relative locations to the CLBs. You can use carry symbols as well as FMAPs and other mapping components in your own schematics. However, knowledge of them is not necessary to use RPMs. Do not create new macros containing carry logic and FMAPs unless you are an expert user. For a description of these components, see the Libraries Guide.
Push into the ADSU4 schematic as follows.
Figure 8.33 Upper Portion of the ADSU4 RPM Schematic | |
Figure 8.34 RLOC Attribute on FMAP Component | |
Close all open schematic or symbol windows except for the top-level Calc schematic window. If you closed the Calc window, re-open it. The Calc schematic appears on the screen.
If your design does not target the XC4000E family, read this section, but do not perform any of the commands.
The XC4000E family devices contain an on-chip clock generator, which makes it unnecessary to use an external circuit for this purpose. The on-board clock circuitry, while not precise, suits designs that do not need a highly accurate clock, such as the Calc design. Refer to the following figure.
Figure 8.35 CLOCKGEN Schematic | |
The CLOCKGEN schematic contains an XC4000E library part, OSC4. This symbol represents the on-chip oscillator that generates nominal clock frequencies of 8 MHz, 500 KHz, 16 KHz, 490 Hz, and 15 Hz. The Calc design uses the 15-Hz output from this component when targeted for XC4000E family designs. The clock output from OSC4 buffers through a BUFG global clock buffer.
XC4000E family devices have eight on-chip clock buffers: one BUFGP (primary global buffer) and one BUFGS (secondary global buffer) in each corner of the device. Although you can use them for other purposes, BUFGPs work best when routing externally-generated clock signals. BUFGSs offer more flexibility; use them to route any large fan-out net, even one internally sourced. A BUFG symbol can represent either type of buffer, and allows the implementation software to choose which type of global buffer works best in each situation. BUFG also facilitates design retargeting to other Xilinx device families, because it can represent any type of global buffer in any family. The BUFG in the Calc design substitutes for a BUFGS during design implementation, because the clock generates internally by the on-chip oscillator. See the Libraries Guide and The Programmable Logic Data Book for more information about global clock buffers for Xilinx devices.
