HDL Flow projects do not require the designation of a top-level design until synthesis. Only VHDL or Verilog source files can be added to an HDL Flow project. VHDL and Verilog source files can be created by the HDL Editor, Finite State Machine Editor, or other text editors. When you initiate the synthesis phase, you designate one of the project's entities (VHDL) or modules (Verilog) as the top-level of the design. The list of entities and modules is automatically extracted from all the HDL source files added to the project. Synthesis processing starts at the designated top-level file. All HDL designs and modules below the top-level file are elaborated and optimized.
HDL designs can contain underlying LogiBLOXs, schematics (EDIF files), ABEL modules, and XNF files that are instantiated in the VHDL and Verilog code as “black boxes.” Black box modules are not elaborated and optimized during synthesis. (Refer to the “HDL Designs with Black Box Instantiation” section for more information on Black Boxes.)
