All-HDL Designs

The following procedure describes the HDL flow for designs that are HDL only, that is, there are no instantiated schematic, LogiBLOX, netlist, or state machine macros.

The Files tab in the Hierarchy Browser area displays the names of all the HDL files in the design.

Creating the Design

1. Open the HDL Editor by clicking the HDL Editor icon in the Design Entry box on the Project Manager's Flow tab.
   
   
   
   
2. When the HDL Editor window appears, you may select an existing HDL file or create a new one. The following steps describe creating a new HDL file with the Design Wizard.
   
   
3. When the HDL Editor dialog box displays, select Use HDL Design Wizard. Click OK.
   
   
4. Click Next in the Design Wizard window.
   
   
5. From the Design Wizard - Language window, select VHDL or Verilog. Click Next.
   
   

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   NOTE

   For top-level ABEL designs, you must use the Schematic Flow.

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6. In the Design Wizard - Name window, enter the name of your design file. Click Next.
   
   
7. Define your ports in the Design Wizard-Ports window by clicking NEW, entering the port name, and selecting its direction. Click Finish. The Wizard creates the ports and gives you a template (in VHDL or Verilog) in which you can enter your design.
   
   
8. Create the design in the HDL Editor. The Language Assistant is available to help with this step. It provides a number of language templates for basic language constructs and synthesis templates for synthesis-oriented implementation of basic functional blocks, such as multiplexers, counters, flip-flops, etc. Access the Language Assistant by selecting Tools Language Assistant.
   
   
9. Add the design to the project by selecting Project Add to Project.
   
   
10. Exit the HDL Editor.
    
    

For more information about HDL designs, see the “HDL Design Entry and Synthesis” chapter or, in the HDL Editor window, select Help Help Topics.

Analyzing Design File Syntax

Syntax is checked automatically when the design is added to the project. You can initiate a syntax check in the HDL Editor by selecting Synthesis Check Syntax after the file is added to the project. You can also analyze syntax by selecting Project Analyze HDL Source Files from the Project Manager.

Use the HDL Error and HDL Warnings tabs in the messages area at the bottom of the Project Manager to view any syntax errors or messages output during analysis.

Performing HDL Behavioral Simulation (Optional)

If you installed an HDL simulation tool such as ACTIVE-VHDL or ModelSIM, you can perform a behavioral simulation of your HDL code. Please refer to the documentation provided with these tools for more information.

Synthesizing the Design

After the design files have been successfully analyzed, the next step is to translate the design into gates and optimize it for a target architecture.

1. Set the global synthesis options by selecting Synthesis Options from the Project Manager. In the Synthesis Options dialog, you can set the following defaults:
   
   
   • Default clock frequency
     
     
   • Export timing constraints to the place and route software
     
     
   • Input XNF bus style
     
     
   • FSM Encoding (One Hot or Binary)
     
     
   • FSM Synthesis Style
     
     
     
     
2. Click OK to close the Synthesis Options dialog
   
   
3. Click the Synthesis icon on the Synthesis button on the Flow tab.
   
   
   
   
4. The Synthesis/Implementation dialog box is displayed.
   
   
   
   
5. Select the name of the top-level VHDL entity or Verilog module. Processing will start from the file named here and proceed through all its underlying HDL modules.
   
   
6. Enter a version name.
   
   
7. Select the target device.
   
   
8. Modify the synthesis processing settings as desired.
   
   
   • Modify the target clock frequency
     
     
   • Select to optimize the design for speed or area
     
     
   • Select the effort level as high or low
     
     
   • Select whether I/O pads should be inserted for the designated top-level module
     
     If you have Foundation Express, you have the following two additional options.
     
     
   • Select Edit Synthesis/Implementation Constraints. Selecting this options pauses synthesis processing after the elaboration phase to allow you to specify constraints (controls) for the design using a constraints editor GUI. This feature is also referred to as the “Express Constraints Editor.” For more information refer to the “Express Constraints Editor (Optional)” section.
     
     
   • Select View Estimated Performance after Optimization. Select this option to view the estimated performance results after design optimization. This feature is also referred as the “Time Tracker.” For more information refer to the “Express Time Tracker^™ (Optional)” section.
     
     
9. Click Run to synthesize the designated top-level HDL design and its underlying HDL modules.
   
   The synthesis compiler automatically includes top-level input and output pads required for implementation (unless instructed not to do so in the Synthesis Settings on the Synthesis/Implementation dialog.)
   
   

Express Constraints Editor (Optional)

The Express Constraints Editor is available with the Foundation Express product only. It allows you to set performance constraints and attributes before optimization of FPGA designs.

1. The Express Constraints Editor window automatically displays during Synthesis processing if you checked the Edit Synthesis/Implementation Constraints box on the Synthesis/Implementation dialog.
   
   Alternatively, you can access the Express Constraints Editor via the Versions tab by right-clicking on a project version in the Hierarchy Browser and then selecting Edit Constraints.
   
   The following figure shows an example of the Clocks tab of the Express Constraints Editor.
   
   

   Figure 5.2 Express Constraints Editor - Clocks Tab

2. Design-specific information is extracted from the design and displayed in device-specific spreadsheets. Click the tabs to access the various spreadsheets.
   
   If you un-checked Insert I/O pads on the Synthesis/Implementation dialog, only the Modules and Xilinx Options tabs are shown. The Clocks, Ports, and Paths tabs apply only to top-level HDL designs.
   
   
3. Right-click on an item in any of the spreadsheets to edit the value, access a dialog box to edit the value, or access a pulldown menu to select a value. Use the online help in the dialog boxes to understand and enter specific constraints and options.
   
   The following figure shows an example of the dialog box accessed when you right click on an output delay value displayed on the Ports tab of the Express Constraints Editor.
   
   

   Figure 5.3 Express Constraints Editor - Ports Tab

4. Optionally, you can import a constraints file (.exc) to use now (click Import Constraints) or you can export the entered constraints to a constraints file (.exc) for reuse (click Export Constraints).
   
   
5. After you finish editing the constraints, click OK to close the Constraints window and continue the synthesis using the specified constraints.
   
   

Express Time Tracker^™ (Optional)

The Express Time Tracker is available with the Foundation Express product only. It allows you view estimated performance results after optimization of your designs.

1. The Optimized (Constraints) window, shown in the figures at the end of this section, automatically displays after Synthesis processing if you checked the View Estimated Performance after Optimization box in the Synthesis/Implementation dialog window.
   
   Alternatively, you can access the Optimized (Constraints) window via the Versions tab by right-clicking on an optimized structure in the Hierarchy Browser and then selecting View Synthesis Results.
   
   
2. Click the tabs to access the performance results in the various spreadsheets.
   
   If you un-checked Insert I/O pads on the Synthesis/Implementation dialog, only the Models and Xilinx Options tabs are shown. The Clocks, Ports, and Paths tabs apply only to top-level HDL designs.
   
   
3. After you finish viewing the results, click OK to close the Optimized (Constraints) window.
   
   

   Figure 5.4 Express Time Tracker - Clocks Tab

   Figure 5.5 Express Time Tracker - Ports Tab

Performing Functional Simulation (Optional)

Functional Simulation may be performed to verify that the logic you created is correct.

1. Open the Logic Simulator by clicking the Functional Simulation icon in the Simulation box on the Project Manager's Flow tab.
   
   
   
   
2. The design is automatically loaded into the simulator. The Waveform Viewer window displays on top of the Logic Simulator window.
   
   
   
   
3. Add signals by selecting Signal Add Signals.
   
   
4. From the Signals Selection portion of the Components Selection for Waveform Viewer window, select the signals that you want to see in the simulator.
   
   
5. Use CTRL-click to select multiple signals. Make sure you add output signals as well as input signals.
   
   
6. Click Add and then Close. The signals are added to the Waveform Viewer in the Logic Simulator screen.
   
   
7. Select Signal Add Stimulators from the Logic Simulator menu. The Stimulator Selection window displays.
   
   
   
   
8. In the Stimulator Selection window, create the waveform stimulus by attaching stimulus to the inputs. For more details on how to use the Stimulus Selection window, click Help.
   
   
9. After the stimulus has been applied to all inputs, click the Simulator Step icon on the Logic Simulator toolbar to perform a simulation step. The length of the step can be changed in the Simulation Step Value box to the right of the Simulation Step box. (If the Simulator window is not open, select View Main Toolbar.)
   
   
   
   
10. Verify that the output waveform is correct. Click the step button repeatedly to continue simulating.
    
    
11. To save the stimulus for future viewing or reuse, select File Save Waveform. Enter a file name with a .tve extension in the File name box of the Save Waveform window. Click OK.
    
    For more information about saving and loading test vectors, select Help Logic Simulator Help Contents from the Logic Simulator window. Then select Simulator Reference Working With Waveforms Saving and Loading Waveforms.
    
    

Implementing the Design

Design Implementation is the process of translating, mapping, placing, routing, and generating a Bit file for your design. Optionally, it can also generate post-implementation timing data.

1. Click the Implementation icon on the Implementation phase button on the Project Manager's Flow tab.
   
   
   
   
2. The Synthesis/Implementation dialog box appears if the design version has been synthesized but no revisions exist. (Refer to the “Design Implementation” chapter for more information on the variations possible when the Implementation phase button is used in the HDL Flow.)
   
   
   
   A revision represents an implementation on the version selected for the Synthesis phase. Modify the name in the Revision Name box, if desired. The other settings are the same ones set for the synthesis phase.
   
   
3. Click the Options button under the Physical Implementation Settings area. The Options dialog box displays.
   
   
4. Choose any desired implementation option. If you are planning on conducting a timing simulation, select the Produce Timing Simulation Data option.
   
   
5. Click OK to return to the Synthesis/Implementation dialog box.
   
   
6. Click Run to implement your design. The Flow Engine displays the progress of the implementation.
   
   The Project Manager displays a status message when Implementation is complete. View the Console tab on the Project Manager window for the results of all stages of the implementation. The Versions tab also indicates the status of the implemented revision.
   
   
7. Click the Versions tab in the Hierarchy Browser area of the Project Manager. Select the current revision. Then select the Reports tab on the Project Manager window to review the reports and logs for that revision of the design.
   
   Click on the Implementation Report Files icon to view the implementation reports. Click on the Implementation Log File icon to view the Flow Engine's processing log.
   
   For more information on the Flow Engine, select Help Foundation Help Contents Flow Engine.
   
   

Verifying the Design (Optional)

After the design has been implemented, the Timing Analyzer or the Timing Simulator can be used to perform a timing analysis on your design. The Timing Analyzer performs a static timing analysis that does not include insertion of stimulus vectors.The Timing Simulator uses input stimulus to run the simulation.

Performing a Static Timing Analysis

1. Click the Timing Analyzer icon in the Verification box on the Project Manager's Flow tab.
   
   
   
   
2. Perform a static timing analysis on mapped or place and routed designs.
   
   

For FPGAs, you can perform a post-MAP or post-place timing analysis to obtain rough timing information before routing delays are added. You can perform a post-implementation timing analysis on CPLDs after a design has been implemented.

For details on how to use the Timing Analyzer, select Help Foundation Help Contents Timing Analyzer.

Performing a Timing Simulation

1. Open the Timing Simulator by clicking the Timing Simulation icon in the Verification box on the Project Managers's Flow tab. The implementation timing netlist will be loaded into the simulator.
   
   
   
   The Waveform Viewer window displays on top of the Logic Simulator window.
   
   
2. Refer to the “Performing Functional Simulation (Optional)” section earlier in this chapter for instructions on simulating the design. (The operation of the simulator is the same for functional and timing simulation.)
   
   
3. If you have already saved test vectors (for instance, in the functional simulation), you may load these vectors into the timing simulator by selecting File Load Waveform.
   
   

Programming the Device

1. Click the Device Programming icon in the Programming box on the Project Manager's Flow tab.
   
   
   
   
2. From the Select Program box, choose the Hardware Debugger, the PROM File Formatter, or the JTAG Programmer. For CPLD designs, use the JTAG Programmer. For instructions, select Help Foundation Help Contents Advanced Tools JTAG Programmer. For FPGA designs, use the JTAG Programmer, Hardware Debugger, or PROM File Formatter. For instructions, select Help Foundation Help Contents Advanced Tools and then select the desired tool.