Development System Reference Guide

About This Manual

The Development System Reference Guide contains information on the software programs in the Xilinx Development System. Generally, the chapters are organized in the following way.

A brief summary of program functions
A syntax statement
A review of the input files used and the output files generated by the program
A listing of the commands, options, or parameters used by the program
Examples of how you can use the program

For an overview of the Xilinx Development System describing how these programs are used in the design flow, see the “Design Flow” chapter.

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this page. You can also directly access some of these resources using the provided URLs.

Resource	Description/URL
Tutorial	Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers Database	Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm
Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
Xcell Journals	Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm
Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm

Manual Contents

The Development System Reference Guide provides detailed information about converting, implementing, and verifying designs in the Xilinx environment. Check the program chapters for information on what program works with each family of FPGA or CPLD device. The following is a brief overview of the contents and organization of the Development System Reference Guide.

Chapter 1, “Introduction,” - Describes some basics that are common to the different Xilinx Development System modules.
Chapter 2, “Design Flow” - Describes the basic design processes: design entry, implementation, and verification.
Chapter 3, “PARTGEN” - Explains how to use the PARTGEN command to obtain information about installed devices and families.
Chapter 4, “NGDBuild,” - NGDBuild performs all of the steps necessary to read a netlist file in XNF or EDIF format and create an NGD (Native Generic Database) file describing the logical design reduced to Xilinx primitives.
Chapter 5, “The User Constraints (UCF) File,” - The UCF File is an ASCII file in which you enter constraints affecting how the logical design is implemented.
Chapter 6, “Using Timing Constraints,” - This chapter describes how you specify timing requirements for your design.
Chapter 7, “The Logical Design Rule Check,” - The Logical DRC (Design Rule Check), is a series of tests run to verify the logical design described by the NGD (Native Generic Database) file.
Chapter 8, “MAP - The Technology Mapper,” - MAP maps the logic defined by an NGD file into FPGA elements such as CLBs, IOBs, and TBUFs.
Chapter 9, “LCA2NCD,” - LCA2NCD translates an LCA file from an earlier Xilinx Development System release to an NCD file.
Chapter 10, “The Physical Constraints (PCF) File,” - The PCF file is an ASCII file containing physical constraints created by the MAP program and physical constraints you enter.
Chapter 11, “DRC - Physical Design Rule Check,” - The physical Design Rule Check (DRC) consists of a series of tests used to discover physical errors in your design.
Chapter 12, “PAR - Place and Route,” - PAR places and routes FPGA designs.
Chapter 13, “PIN2UCF,” - PIN2UCF generates pin locking constraints in a UCF file by reading a a placed NCD file for FPGAs or GYD file for CPLDs.
Chapter 14, “TRACE,” - TRACE (Timing Reporter and Circuit Evaluator) performs static timing analysis of the physical design based on input timing constraints.
Chapter 15, “SPEEDPRINT” - SPEEDPRINT lists block delays for a specified device and its speed grades.
Chapter 16, “BitGen,” - BitGen creates a configuration bitstream for an FPGA design.
Chapter 17, “PROMGen,” - PROMGen converts a configuration bitstream (BIT) file into a file that can be downloaded to a PROM. PROMGen also combines multiple BIT files for use in a daisy chain of FPGA devices.
Chapter 18, “NGDAnno,” - NGDAnno annotates timing information found in the physical NCD design file back to the logical NGD file.
Chapter 19, “NGD2EDIF,” - NGD2EDIF converts an NGD file to an EDIF file for use in simulation.
Chapter 20, “NGD2VER,” - NGD2VER converts an NGD file to a Verilog HDL file for use in simulation.
Chapter 21, “NGD2VHDL,” - NGD2VHDL converts an NGD file to a VHDL file for use in simulation.
Chapter 22 “XFLOW” - XFLOW is a command tool that runs the full suite of implementation and simulation flows.
Appendix A, “Xilinx Development System Files,” - This appendix gives an alphabetic listing of the files used by the Xilinx Development System.
Appendix B, “EDIF2NGD, XNF2NGD, and NGDBuild,” - This appendix describes the netlist readers (EDIF2NGD and XNF2NGD) and how they interact with NGDBuild.

Conventions

This manual uses the following typographical and online document conventions. An example illustrates each typographical convention.

Typographical

The following conventions are used for all documents.

Courier font indicates messages, prompts, and program files that the system displays.

speed grade: -100
Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].

rpt_del_net=

Courier bold also indicates commands that you select from a menu.

File Open
Italic font denotes the following items.
- Variables in a syntax statement for which you must supply values
  
  edif2ngd design_name
- References to other manuals
  
  See the Development System Reference Guide for more information.
- Emphasis in text
  
  If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.

edif2ngd [option_name] design_name
Braces “{ }” enclose a list of items from which you must choose one or more.

lowpwr ={on|off}
A vertical bar “|” separates items in a list of choices.

lowpwr ={on|off}
A vertical ellipsis indicates repetitive material that has been omitted.

IOB #1: Name = QOUT' IOB #2: Name = CLKIN' . . .
A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.

allow block block_name loc1 loc2 ... locn;

Online Document

The following conventions are used for online documents.

Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.