DRC

The physical Design Rule Check (DRC) consists of a series of tests to discover physical errors and some logic errors in the design. Three Xilinx Development System modules employ physical DRC. The physical DRC is used in the following ways.

• MAP automatically runs physical DRC after it has mapped the design.
  
  
• PAR (Place and Route) automatically runs physical DRC on nets when it routes the design.
  
  
• You can run physical DRC from within the FPGA Editor. The DRC also runs automatically after certain FPGA Editor operations (for example, when you edit a logic cell or when you manually route a net). For a description of how the DRC works within the FPGA Editor, see the “Physical Design Rule Check (DRC)” section of the FPGA Editor Guide.
  
  
• BitGen, which creates a a BIT file for programming the device, automatically runs physical DRC.
  
  
• You can run physical DRC from the UNIX or DOS command line.