Verifying Your Design

You can use the following FPGA Editor tools to verify your designs.

• Physical Design Rule Check (DRC)
  
  
• Delay Calculator
  
  

This section contains the following topics.

• “Physical Design Rule Check (DRC)”
  
  
• “Delay Calculator”
  
  
• “TRACE”
  
  

Physical Design Rule Check (DRC)

Physical Design Rule Check (DRC) is a series of tests to find logical and physical errors in your design. Physical DRC is applied to the FPGA Editor and BitGen. In addition to running in the FPGA Editor, the DRC runs during these conditions.

• You select the Run DRC toolbar icon in the Block window
  
  
• During manual routing
  
  
• Whenever you add pins to a net
  
  

The DRC runs in the background. Results of the DRC are written into the history area. DRC error messages indicate faulty or incomplete routing or component logic.

DRC runs can produce a large number of messages. Because the history area can only contain a limited number of characters, you may not be able to scroll to messages at the beginning of a DRC run or to messages from previous runs. If you want to view them, use a text editor to view the contents of the log file (design_name.out) for your session. See the “Recovering a Terminated FPGA Editor Session” section. When you exit the FPGA Editor, the log file is renamed design_name_fpga_editor_YYMMDD_HHMMSS.log, where Y is year, M is month, D is day, H is hour, M is minute, and S is second.

Note: When you run the DRC on selected objects, the objects are deselected if the Automatic Deselect Option main window property is turned On. If the option is turned Off, the objects remain selected after the DRC runs.

The DRC tests performed follow these rules.

• If you select one or any combination of net names, routes, or net pins, the Net Check is performed.
  
  
• If you select one or more components, the Block Check is performed.
  
  
• If you select objects that combine the first and second types, both Net Check and Block Check are performed.
  
  

Running a DRC

To run a DRC, follow these steps.

1. Select the design objects for the DRC run.
   
   Select any combination of components, net pins, route segments, or nets. To check all objects, do not select any objects.
   
   
2. Select Tools DRC Setup to display the DRC dialog box, as shown in the “DRC Dialog Box” figure of the “Menu Commands” chapter.
   
   
3. Select the corresponding button to perform a Net Check, Block Check, Chip Check, or All Checks
   
   You can select only one.
   
   
4. Select the corresponding button to perform the DRC on All Objects in your design or only on Selected Objects.
   
   
5. Select All Messages for all DRC messages, errors and warnings or Error Messages.
   
   
6. Click Apply or OK.
   
   The DRC tests are performed on the specified objects.
   
   

Delay Calculator

Delay is the time that it takes to propagate a signal from a driver pin to a load pin. If not otherwise indicated, delay values are given in nanoseconds (ns). The Delay Calculator tool calculates and displays the delay associated with load and driver pins in a given net or path.

Calculating Net Delay

You can either find the delay for all pins in the net or for specific pins.

To find the delay for all pins in a net, follow these steps.

1. Select a net name from the List window.
   
   
2. Select Delay in the User toolbar.
   
   If the net is fully or partially routed, a list of pins appears in the history area, along with their associated delays. If the net is unrouted, each pin is listed as “unrouted.”
   
   
3. Select Attrib in the User toolbar to display the Net Properties property sheet.
   
   
4. Select the Pins page to display the delays for associated pins.
   
   

If a blank space appears next to a pin name, either in the pin list or in the history area, the pin is the net driver that has no delay or the pin is unrouted. A tilde (~) appearing with a delay, indicates that the value shown is an approximate.

Note: When you display delays for all of the pins in a net, the net is deselected if the Automatic Deselect Option in the Main Properties property sheet is turned On.

To display the delays for selected pins in a net, use the mouse to select the specific pins. If the net is fully or partially routed, the delays for the selected pins are automatically displayed in the history area. If the net is unrouted, no delays are displayed.

Calculating Path Delay

To display the delay between two pins in a path follow these steps.

1. Select the two pins with the mouse.
   
   
2. Select Delay in the User toolbar.
   
   The path delay between the two pins is displayed in the history area. If there are multiple paths between the two pins, the path with the maximum delay appears. If Auto Highlight is enabled, the path between the pins is highlighted.
   
   

TRACE

You can run TRACE (Timing Reporter and Circuit Evaluator) in the FPGA Editor to visualize timing errors and to make modifications without going back and forth between the FPGA Editor and TRACE.

Functions performed by TRACE in the FPGA Editor are the same as those outside of the FPGA Editor with a few exceptions, as noted in this section.

TRACE functionality within the FPGA Editor includes the following.

• Specify error or verbose report types
  
  
• Limit the number of errors reported per constraint in the timing error and verbose reports. The summary report is not supported in the FPGA Editor
  
  

Input and Output Files

• Input to TRACE is your currently loaded design file and the constraint file
  
  
• Output is sent to the history area, unless you specify otherwise, and to the OUT (log) file instead of to a timing report (TWR) file.
  
  

Running TRACE from the Tools Menu

To run TRACE from the Tools menu follow these steps.

1. Select Tools Trace Setup and Run to display the dialog box shown in the “Trace Dialog Box” figure of the “Menu Commands” chapter.
   
   
2. Make your entries in the TRACE dialog box as described in the “Trace Dialog Box Options” section of the “Menu Commands” chapter.
   
   
3. Click OK or Apply.
   
   TRACE runs timing analysis, and the Trace Summary dialog box appears, as shown in the “Trace Summary Dialog Box” figure of the “Menu Commands” chapter. This dialog box lists information on any constraints that failed to meet timing, as described in the “Trace Summary Dialog Box Options” section of the “Menu Commands” chapter.
   
   
4. For additional timing information on any of the constraints listed in the Summary dialog box, click on the listed constraint. The TRACE Errors dialog box appears, as shown in the following figure.
   
   

Figure 3.8 TRACE Errors Dialog Box

This dialog box contains the following fields.

• Constraint
  
  Displays the constraint. You cannot modify this field.
  
  
• Summary
  
  Displays a one-line summary of the constraint. You cannot modify this field.
  
  
• Delay/Name
  
  Delay specifies the delay of the selected path in nanoseconds. Name specifies the start and end point for the path.
  
  
• Report
  
  Outputs the detailed TRACE report for the selected path to the history area and to the OUT (log) file.
  
  
• Unhilite
  
  Unhighlights the selected path in the FPGA Editor window.
  
  
• Hilite
  
  

Highlights the selected path, using the specified color.