Guided PAR

You can use guide files to modify your design incrementally or you can integrate your design with PCI Core guide files. The following sections describe both types of guided PAR use.

Incremental Designs

An optional guide design file can be fed into PAR. The guide file is an NCD file which is used as a template for placing and routing the input design. This is useful if minor incremental changes have been made to create a new design. To increase productivity, you can use your last design iteration as a guide design for the next design iteration, that is, your output NCD file becomes the guide design file for your next iteration of the design (see the following figure).

Figure 12.4 Guided PAR for Incremental Design

Two command line options control guided PAR. The -gf option specifies the NCD guide file, and the -gm option determines whether exact mode or leveraged mode is used to guide PAR.

The guide design is used as follows.

• If a component in the new design is constrained to the same location that a component is placed in the guide file, this component will be defined as matching.
  
  
• If a component in the new design has the same name as a component in the guide design, that component will match the guide component.
  
  
• If a signal in the new design has the same name as a signal in the guide design, the signal will match the guide signal.
  
  
• Any matching component in the new design will be placed in the site corresponding to the location of the matching guide component, if possible.
  
  
• Matching component's pins will be swapped to match those of the guide component with regard to matching signals, if possible.
  
  
• All of the connections between matching driver and load pins of the matching signals will have the routing information preserved from the guide file, if possible.
  
  

When PAR runs using a guide design as input, PAR first places and routes any components and signals that fulfill the matching criteria described above. Then PAR places and routes the remainder of the logic.

To place and route the remainder of the logic, PAR does the following.

• If you have selected exact guided PAR (by entering the -gm exact option on the PAR command line), the placement and routing of the matching logic are locked. Neither placement nor routing can be changed to accommodate the additional logic.
  
  
• If you have selected leveraged guided PAR (by entering the -gm leverage option on the PAR command line), PAR tries to maintain the placement and routing of the matching logic, but changes placement or routing if it is necessary in order to place and route to completion and achieve your timing constraints (if possible).
  
  Some cases where the leveraged mode is necessary are as follows:
  
  
  • You have added logic that makes it impossible to meet your timing constraints without changing the placement and routing in the guide design.
    
    
  • You have added logic that demands a certain site or certain routing resource, and that site or routing resource is already being used in the guide design.
    
    As one example of this condition, in XC4000EX devices TBUFs must be routed along long lines. If you add TBUFs to an XC4000EX design but your guide design uses too many of the required long lines, you are not able to route this design to completion unless you use the leveraged option.
    
    

If you enter a -gm (guide mode) option but do not specify a guide file with the -gf option, PAR is guided by the placement and routing information in the input NCD file. Depending on whether you specify exact mode or leveraged mode, PAR locks the input NCD's existing placement and routing (exact mode), or tries to maintain the placement and routing, but modifies them in an effort to place and route to completion and achieve your timing constraints (leveraged mode).

Note: For Verilog or VHDL netlist input designs, re-synthesizing modules typically cause signal and instance names in the resulting netlist to be significantly different from the netlist obtained in earlier synthesis runs. This occurs even if the source level Verilog or VHDL code only contains a small change. Because guided PAR depends on signal and component names, synthesis designs often have a low "match rate" when guided. Therefore, guided PAR is not recommended for most synthesis-based designs, although there may be cases where it could be a successful alternative technique.

PCI Cores

For the 2.1i release, you can use a guide file to add a PCI Core, which is a standard I/O interface, to your design. The PCI Core guide file must already be placed and routed. PAR only places and routes the signals that run from the PCI Core to the input NCD design; it does not place or route any portion of the PCI Core. You can also use the resulting design (PCI Core integrated with your initial design) as a guide file. However, you must then use the exact option for -gm, not leverage, when generating a modified design.

Guided PAR supports more precise matching of placement and routing of PCI Cores that are used as reference designs in a guide file:

• Components locked in the input design are guided by components in the reference design of a guide file in the corresponding location.
  
  
• Signals that differ only by additional loads in the input design will have the corresponding pins routed according to the reference design in the guide file.
  
  
• Guide summary information in the PAR report describes the amount of logic from the reference design that matches logic in the input design.
  
  

For detailed information about designing with PCI, refer to the Xilinx PCI web page (http://www.xilinx.com/products/logicore/pci/pcilit.htm).