BitGen Options

Following is a description of the command line options and how they affect the behavior of BitGen.

Note: For a complete description of the Xilinx Development System command line syntax, see the “Command Line” section of the “Introduction” chapter.

Options for the BitGen command are as follows.

-a (Tie All Interconnect)

Used with the -t option to force tiedown to fail if all nodes are not tied. This option also allows tiedown to implement user signals.

-b (Create Rawbits File)

Create a "rawbits" (file_name.rbt) file. The rawbits file consists of ASCII ones and zeros representing the data in the bitstream file.

If you are using a microprocessor to configure a single FPGA, you can include the rawbits file in the source code as a text file to represent the configuration data. The sequence of characters in the rawbits file is the same as the sequence of bits written into the FPGA.

-d (Do Not Run DRC)

Do not run DRC (Design Rule Check). Without the -d option, BitGen runs a DRC and saves the DRC results in two output files: the BitGen report file (file_name.bgn) and the DRC file (file_name.drc). If you enter the -d option, no DRC information appears in the report file and no DRC file is produced.

Running DRC before a bitstream is produced detects any errors that could cause the FPGA to malfunction. If DRC does not detect any errors, BitGen produces a bitstream file (unless you use the -j option described in the “-j (No BIT File)” section).

You cannot disable the DRC with the -d option if you have specified a -t (Tie Unused Interconnect) option. The DRC always runs if you specify -t.

-f (Execute Commands File)

-f command_file

The -f option executes the command line arguments in the specified command_file. For more information on the -f option, see the “-f Option” section of the “Introduction” chapter.

-g (Set Configuration)

The -g option specifies the startup timing and other bitstream options for Xilinx FPGAs. The settings for the -g option depend on the design's architecture. These settings are described in the following sections.

• “-g (Set Configuration - XC3X00 Devices)”
  
  
• “-g (Set Configuration - XC4000 and Spartan)”
  
  
• “-g (Set Configuration - XC5200 Devices)”
  
  

• “-g (Set Configuration - Virtex and Spartan2 Devices)”
  
  

-g (Set Configuration - XC3X00 Devices)

The -g option has sub-options that represent settings you use to set the configuration for an XC3X00A/L design. These options have the following syntax.

bitgen -g option:setting

For example, to set the input signal thresholds to CMOS level instead of TTL level, use the following syntax.

bitgen -g inputs:CMOS

The following sections describe the startup sequences for the -g option applied to an XC3X00 design.

Enables or disables internal pull-up on the DONE/!PROGRAM (D/!P) pin. The Pullnone setting indicates there is no connection to the pull-up.

Use this option only if you are planning to connect an external pull-up resistor to this pin. The internal pull-up resistor has a value of 2 to 8 kilohm and is automatically connected if you do not use this option.
The D/!P pins configure an open-drain driver that requires a pull-up resistor to indicate the end of the configuration.

Releases the DONE/!PROGRAM (D/!P) pin one Cclk cycle before the IOBs become active (Before setting) or one Cclk cycle after the IOBs become active (After setting).

The After setting clearly indicates the end of the configuration process. The Before setting can be used to de-activate external configuration drivers so that they do not contend with active outputs on the same pin. The use of After would create a 1-Cclk-period contention. The alternative, using the LDC output, might cause a short contention spike. Before avoids these problems.

This option sets the FPGA design input-signal thresholds to TTL or CMOS level for interface capability. CMOS improves noise immunity and reduces static power consumption.

The special-purpose clock inputs, TCLKIN, BCLKIN, and !PWRDN always require CMOS-level signals, even if the FPGA design input thresholds are specified as TTL compatible.

Determines how length count is calculated to control when the device changes from configuration to user operation. The two methods of calculating length count, DONE Alignment and Length Count Alignment, are discussed in The Programmable Logic Data Book. The FPGA Configuration Guidelines Application Note also contains length count information.

This option specifies crystal oscillator options for XC3X00 series devices. The crystal oscillator is associated with the auxiliary clock buffer in the lower-right corner of the die.

The Disable option disables the FPGA crystal oscillator; Enable enables it. The EnableDiv2 option enables the oscillator and divides the crystal output frequency by two in order to guarantee a symmetrical clock signal.

This option specifies readback options for XC3X00 families. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. Once you give the readback command, external logic must drive the Cclk input to read back each data bit. The readback data appears on the !RDATA pin.

The Disable option disables readback. The Once option enables a one-time readback and Command enables readback on command.

The Disable and Once options are used for design security. The Once option allows only one readback, typically performed during manufacturing. After this, readback can never be invoked again.
If the FPGA device is powered by a standby battery and the configuration source is removed, the FPGA design configuration data is completely secure from being read or copied.

Removes INTERNAL RESET one clock cycle before or one clock cycle after the IOB becomes active.

When you specify the After setting, the outputs go active while all internal flip-flops are still being held in Reset. When you specify the Before setting, the internal logic becomes operational before the outputs go active.

-g (Set Configuration - XC4000 and Spartan)

Note: For Spartan2 -g options, see the “-g (Set Configuration - Virtex and Spartan2 Devices)” section.

This option specifies the startup timing and other bitstream options for the XC4000E/L, XC4000EX/XL/XV, and Spartan devices. Timing sequences are predefined startup defaults that use the following syntax.

bitgen -g timing_sequence

There are four valid startup sequences: Cclk_Nosync, Cclk_Sync, Uclk_Nosync, and Uclk_Sync. These startup sequences are described in the next section. For more information about startup timing, refer to The Programmable Logic Data Book.

The default startup sequence for the -g option is Cclk_Nosync. This startup sequence makes an XC4000 or Spartan device compatible with an XC3X00 device that is set for early Done and late Reset. Enter the following,

bitgen -g cclk_nosync

The -g option has sub-options that represent settings you use to set the configuration for an XC4000 or Spartan design. These options have the following syntax.

bitgen -g option:setting

For example, to enable Cyclic Redundancy Checking (CRC), use the following syntax.

bitgen -g crc:enable

The following sections describe the startup sequences for the -g option.

This section describes the four predefined startup sequences and their defaults; then it describes the options, their settings, and their defaults.

Note: When mixing devices, the one with the latest “finished point” should be the master. The master stops clocking when it reaches the finished point. See The Programmable Logic Data Book for more information.

This is the default startup sequence for the -g option. Selecting this sequence causes the following defaults to take effect.

This startup sequence makes an XC4000, Spartan, or XC5200 device consistent with an XC3X00 device set for early Done and late Reset.

Selecting this sequence causes the following defaults to take effect.

This startup sequence is the most consistent with the XC3X00 devices, since it synchronizes the release of GSR and I/Os to the external DoneIn signal. This startup sequence makes an XC4000 or Spartan device consistent with an XC3X00 device set for early Done and late Reset.

Selecting this sequence causes the following defaults to take effect.

This startup sequence makes XC4000 or Spartan devices inconsistent with XC3X00 devices if they are in the same daisy chain, since the release of Done is synchronized to an external User Clock. There is no synchronization of I/Os or GSR to DoneIn.

Selecting this sequence causes the following defaults to take effect.

This startup sequence makes XC4000 or Spartan devices inconsistent with XC3X00 devices if they are in the same daisy chain, since the release of Done is synchronized to an external User Clock. I/Os and GSR are synchronous to the clocks following DoneIn.

When using Uclk_Sync or Uclk_Nosync, you must provide a user clock to finish the configuration sequence. Without a user clock the FPGA will not configure.

Sub-Options for Startup Sequence (-g Option)

The sub-options available with the four startup sequences are described below. These sub-options use the -g option:setting syntax.

Determines the number of address lines (18 or 22) used for device configuration. The 22 setting activates four extra device pins as configuration address lines.

When disabled, BSCAN_Config inhibits the BSCAN-based configuration after the device is successfully configured. This feature allows board testing without the risk of reconfiguring XLA devices by toggling the TCK/TMS/TDI/TDO lines.

When enabled, BSCAN_Status allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. Previously, there was no direct method for determining if a BSCAN-based configuration was successful.

If set to On, this option allows a 3.3V device circuitry to tolerate 5V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, ensure that On is set. For any circuitry that operates exclusively on 3.3V, such as in a laptop computer, set the option to Off. The Off option reduces power consumption.

Selects the configuration clock rate. There are two choices: slow or fast. Slow is equivalent to 1 MHz, and fast is equivalent to 8 MHz (nominal).

Enables or disables Cyclic Redundancy Checking (CRC) on a chip-by-chip basis during configuration.

Selects the event that activates the FPGA Done signal. There are a maximum of four events that you can select from at one time. These events are Cclk edges or external (user) clock edges.

The actual options available at any time depend on the selections made for StartupClk and SyncToDone.

Valid settings for DoneActive are as follows.

Enables or disables internal pull-up on the DONE pin. The Pullnone setting indicates there is no connection to the pull-up.

When enabled, ExpressMode creates a unique type of bitstream for configuration.

Selects the event that releases the internal set-reset to the latches and flip-flops. You can select one of nine events: a Cclk edge, an external (user) clock edge, or the external signal DoneIn. Only some of these events become options at one time depending on the combination of StartupClk and SyncToDone selected.

Valid settings for GSRInactive are as follows.

Sets the input threshold level for IOBs.

The LC_Alignment option determines how length count is calculated to control when the device changes from configuration to user operation. The two methods of calculating length count, DONE Alignment and Length Count Alignment, are discussed in the Configuration section of the The Programmable Logic Data Book. The FPGA Configuration Guidelines Application Note also contains length count information.

Adds a pull-up or a pull-down to the M0 (Mode 0) pin. Selecting one option enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Adds a pull-up or a pull-down to the M1 (Mode 1) pin. Selecting one option enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Adds a pull-up or a pull-down to the M2 (Mode 2) pin. Selecting one option enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Sets the output level for IOBs.

Selects the event that releases the I/O from 3-state condition and turns the configuration related pins operational. There are a maximum of four events that you can select from at one time. These events are selected from a group of Cclk edges, a group of external (user) clock edges, and the external signal DoneIn. The actual options available at any time depend on the selections made for StartupClk and SyncToDone.

Valid settings for OutputsActive are as follows.

Enables or disables internal pull-up on the PowerDown pin. The Pullnone setting indicates there is no connection to the pull-up.

Enables or disables aborting the readback sequence during the readback sequence.

Enables or disables readback of configuration bitstream.

Sets the readback clock to be CClk or to a user-supplied clock (from a net inside the FPGA that is connected to the `i' pin of the RDCLK schematic block).

Note: In modes where CClk is an output, the pin is driven by the internal oscillator.

Selects a user-supplied clock or the internal Cclk for controlling the post-configuration startup phase of the FPGA initialization.

Note: In modes where Cclk is an output, the pin is driven by the internal oscillator.

Synchronizes the I/O startup sequence to the external DoneIn signal.

Adds a pull-up, a pull-down, or neither to the TDO pin (Test Data Out for Boundary Scan). Selecting one option enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

-g (Set Configuration - XC5200 Devices)

The -g option has sub-options that represent settings you use to set the configuration for an XC5200 design. These options have the following syntax.

bitgen -g option:setting

For example, to enable Cyclic Redundancy Checking (CRC), use the following syntax.

bitgen -g crc:enable

The following sections describe the startup sequences for the -g option.

Enable or disable reconfiguration via boundary scan.

Enable or disable reading back configuration data via boundary scan.

Selects the configuration clock rate. There are three choices: slow, med, and fast. Slow is equivalent to .75 MHz, med is equivalent to 6 MHz, and fast is equivalent to 12 MHz (nominal).

Enables or disables Cyclic Redundancy Checking (CRC) on a chip-by-chip basis during configuration.

This option sets the FPGA design input-signal thresholds to TTL or CMOS level for interface capability. CMOS improves noise immunity and reduces static power consumption.

The special-purpose clock inputs, TCLKIN, BCLKIN, and !PWRDN always require CMOS-level signals, even if the FPGA design input thresholds are specified as TTL compatible.

Selects the event that activates the FPGA Done signal. There are a maximum of four events that you can select from at one time. These events are Cclk edges or external (user) clock edges.
The actual options available at any time depend on the selections made for StartupClk and SyncToDone.

Valid settings for DoneActive are as follows.

Enables or disables internal pull-up on the DONE pin. The Pullnone setting indicates there is no connection to the pull-up.

Selects the event that releases the internal set-reset to the latches and flip-flops. You can select one of nine events: a Cclk edge, an external (user) clock edge, or the external signal DoneIn.

Only some of these events become options at one time depending on the combination of StartupClk and SyncToDone selected.

Valid settings for GSRInactive are as follows.

Sets the input threshold level for IOBs.

The LC_Alignment option determines how length count is calculated to control when the device changes from configuration to user operation. The two methods of calculating length count, DONE Alignment and Length Count Alignment, are discussed in the Configuration section of The Programmable Logic Data Book. The FPGA Configuration Guidelines Application Note also contains length count information.

Determines whether the XC5200 oscillator is driven by the internal 16-MHz clock (CClk setting) or by a user clock (UserClk setting). If you specify UserClk, the clock must be connected to the OSC.CK pin of the device's OSC component.

Selects the event that releases the I/O from 3-state condition and turns the configuration related pins operational. There are a maximum of four events that you can select from at one time. These events are selected from a group of Cclk edges, a group of external (user) clock edges, and the external signal DoneIn.
The actual options available at any time depend on the selections made for StartupClk and SyncToDone.

Valid settings for OutputsActive are as follows.

Enables or disables internal pull-up on the !PROGRAM pin. The pull-up affects the pin after configuration. The Pullnone setting indicates there is no connection to the pull-up.

Enables or disables aborting the readback sequence during the readback sequence.

Enables or disables readback of configuration bitstream.

Sets the readback clock to be CClk or to a user-supplied clock (from a net inside the FPGA that is connected to the `i' pin of the RDCLK schematic block).

Note: In modes where CClk is an output, the pin is driven by the internal oscillator.

Selects a user-supplied clock or the internal Cclk for controlling the post-configuration startup phase of the FPGA initialization.

Note: In modes where Cclk is an output, the pin is driven by the internal oscillator.

Synchronizes the I/O startup sequence to the external DoneIn signal.

-g (Set Configuration - Virtex and Spartan2 Devices)

The -g option has sub-options that represent settings you use to set the configuration for a Virtex or Spartan2 design. These options have the following syntax.

bitgen -g option:setting

For example, to enable Readback, use the following syntax.

bitgen -g Readback

The following sections describe the startup sequences for the -g option.

This option allows you to perform Readback by the creating the necessary bitstream.

Virtex and Spartan2 use an internal oscillator to generate the configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate for this clock.

Use these options to add delays to the global clocks. You should not use this option unless instructed by Xilinx.

The startup sequence following the configuration of a device can be synchronized to either Cclk, a User Clock, or the JTAG Clock. The default is Cclk.

• Cclk
  
  Enter Cclk to synchronize to an internal clock provided in the FPGA device.
  
  
• UserClk
  
  Enter UserClk to synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol.
  
  
• Jtag Clock
  
  Enter JtagClk to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.
  
  

  Architectures:	Virtex, Spartan2
  Settings:	Cclk (pin - see Note), UserClk (user-supplied), JtagCLK
  Default:	Cclk

  
  
  
  

  Note: In modes where Cclk is an output, the pin is driven by an internal oscillator.

Selects which clock to synchronize to at the end of power up.

Adds an internal pull-up to the Cclk pin. The Pullnone setting disables the pullup.

Adds an internal pull-up to the DonePin pin. The Pullnone setting disables the pullup.

Use this option only if you are planning to connect an external pull-up resistor to this pin. The internal pull-up resistor is automatically connected if you do not use this option.

Enables this output power-down status pin.

The M0 pin is used to determine the configuration mode. Adds an internal pull-up, pull-down or neither to the M0 pin. The following settings are available. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M0 pin.

The M1 pin is used to determine the configuration mode. Adds an internal pull-up, pull-down or neither to the M1 pin. The following settings are available. The default is PullUp.

Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M1 pin.

The M2 pin is used to determine the configuration mode. Adds an internal pull-up, pull-down or neither to the M2 pin. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M2 pin.

Adds an internal pull-up to the PDStatusPin pin. The Pullnone setting disables the pullup.

Use this option only if you are planning to connect an external pull-up resistor to this pin.

Adds an internal pull-up to the input PowerdownPin pin. The Pullnone setting disables the pullup.

Use this option only if you are planning to connect an external pull-up resistor to this pin.

Adds an internal pull-up to the ProgPin pin. The Pullnone setting disables the pullup. The pull-up affects the pin after configuration.

Adds a pull-up, a pull-down or neither to the TCK pin, the JTAG test clock. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Adds a pull-up, a pull-down, or neither to the TDI pin, the serial data input to all JTAG instructions and JTAG registers. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Adds a pull-up, a pull-down, or neither to the TdoPin pin, the serial data output for all JTAG instruction and data registers. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Adds a pull-up, pull-down, or neither to the TMS pin, the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down.

Selects the Startup phase that releases the internal set-reset to the latches, flip-flops, and BRAM output latches. The Done setting releases GSR when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes.

Keep should only be used when partial reconfiguration is going to be implemented. Keep prevents the configuration state machine from asserting control signals that could cause the loss of data.

Selects the Startup phase that asserts the internal write enable to flip-flops, LUT RAMs, and shift registers. It also enables the BRAMs. Before the Startup phase both BRAM writing and reading are disabled.The Done setting asserts GWE when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes. The Keep setting is used to keep the current value of the GWE signal.

Selects the Startup phase that releases the internal tristate control to the IO buffers. The Done setting releases GTS when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes

Selects the Startup phase to wait until DLLs lock. If NoWait is selected, the Startup sequence does not wait for DLLs.

Selects the Startup phase that activates the FPGA Done signal. Done is delayed when DonePipe=Yes.

This option is needed for Readback and Partial Reconfiguration using the configuration pins. It determines the data bus width and which IOBs are always in Configuration mode. These IOBs will be excluded from general use.

The X8 setting must be selected to enable Readback.

Select X1 for serial modes or X8 for Super8 mode. The following table illustrates which pins are persistent in serial and Super8 configurations.

This option actively drives CFG_DONE (Done) high as opposed to using pullup.

This option is intended for use with FPGAs being set up in a high-speed daisy chain configuration.When set to Yes, the FPGA waits on the CFG_DONE (DONE) pin to go High and then waits for the first clock edge before moving to the Done state.

Selecting Level1 disables Readback. Selecting Level2 disables Readback and Partial Reconfiguration.

You can enter up to an 8-digit hexadecimal code in the User ID register. You can use the register to identify implementation revisions.

-h or -help (Command Usage)

-h architecture

Displays a usage message for BitGen. The usage message displays all of the available options for BitGen operating on the specified architecture.

-j (No BIT File)

Do not create a bitstream file (.bit file). This option is generally used when you want to generate a report without producing a bitstream. For example, if you wanted to run DRC without producing a bitstream file, you would use the -j option.

Note: The .msk or .rbt files may still be created.

-l (Create a Logic Allocation File)

This option creates an ASCII logic allocation file (design.ll) for the selected design. The logic allocation file indicates the bitstream position of latches, flip-flops, and IOB inputs and outputs.

In some applications, you may want to observe the contents of the FPGA internal registers at different times. The file created by the -l option helps you identify which bits in the current bitstream represent outputs of flip-flops and latches. Bits are referenced by frame and bit number within the frame.

The Hardware Debugger uses the design.ll file to locate signal values inside a readback bitstream.

-m (Generate a Mask File)

Creates a mask file. This file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA.

-n (Save a Tied design)

This command is used with the -t option (described below) to save the tied NCD file as _file_name.ncd (note the underscore in front of the file name). The tied design file is placed in the same directory as the output file. It has the same root name as the output file with an .ncd extension. If you do not specify an output file, the tied design file is placed in the input file's directory and is named _file_name.ncd, where _file_name is the root name of the input file. Use TRACE to run timing analysis on the tied design. You can also use the FPGA Editor to check the effects of the tiedown. This option is not supported for Virtex or Spartan2.

-t (Tie Unused Interconnect)

This option causes all unused interconnect to be tied to a logic low or to a known level, keeping internal noise and power consumption to a minimum. When you use the -t option, DRC runs first (before tiedown). BitGen terminates if any DRC error occurs. A DRC warning does not cause the bitstream generation program to abort, but it may cause tiedown to fail.

After DRC, the -t option does the following.

• Ties all possible unused interconnect to tie sites or unused CLB outputs and configures those outputs with a logic low (F=0 or G=0)
  
  
• Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical
  
  
• Attempts to tie remaining interconnect to the global or to the auxiliary clock buffer outputs if unused (only in conjunction with the -a option)
  
  

The only condition under which tie will add interconnect to a “critical” net is if you use the -u option (allowing interconnect to be added to critical nets as a “last resort”). A “critical” net is one with a priority greater than 3.

The -t option does not add an XC4000 or XC5200 tristate buffer input (I) pin or tristate (T) pin to a net.

When you add interconnect to used CLB or buffer outputs, delays may be added on any net to which the outputs are connected. To prevent the added delay, assign the net a priority greater than 3. You can do this through the physical constraints file or through the FPGA Editor. See the PRIORITIZE physical constraint in the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide. Note that flagging too many nets as critical could cause the tiedown to fail. When an interconnect is tied to a user-defined net, you get a message giving the number of nodes added to the net. Delay characteristics for the net associated with that source may change. (Only in conjunction with the -a option)

When certain pins cannot be tied, you receive a warning message supplying information about the design's untied interconnect.

To remove the obstacles that have caused tiedown to fail, look carefully at nets close to an untied PIP. An input pin could have multiple input PIPs, and all of them could source the pin. If each of these PIPs is associated with a critical net, they are not used, and the input pin is left untied. To correct the problem, make one of the nets “non-critical.” Do this by removing the PRIORITIZE constraint from the net in the PCF file or in the FPGA Editor. Then run TRACE (the timing analysis program) and evaluate any delay that might have been added to the net. (Only in conjunction with the -a option)

If you use the -n option, the tied design is saved in a file _file_name.ncd (note the underscore before the file name). You can load the file into the FPGA Editor and examine the results of tiedown. You can look at all of the original nets that have been affected by tiedown and the net delays before and after tiedown.

Like unused internal interconnect, unused external I/O pins on the chip must also have defined signal levels, that is, they must not be in a floating condition. In XC4000E/EX FPGAs, unused IOBs are automatically pulled HIGH with pull-up resistors.

Partial tiedown is the new default. Tiedown will print the number of untied nodes and then continue. See the -a option also. Partial tiedown never ties to user signals.

This option is not supported for Virtex or Spartan2.

-u (Use Critical Nets Last)

Because of possible added delay, tiedown does not add interconnect to any net that has been assigned a priority greater than 3. This option allows interconnect to be added to critical nets as a “last resort.”

This option is not supported for Virtex or Spartan2.

-w (Overwrite Existing Output File)

Enables you to overwrite an existing BIT, LL, MSK, or RBT output file.