Back-Annotation

In the back-annotation process, physical design information, including timing values, is distributed back to the logical design for back-end simulation.

In the Xilinx Development System, back-annotation for FPGA designs operates as follows.

• NGDAnno distributes delays, setup and hold times, and pulse widths in the physical NCD design file onto the logical design view represented in the NGD file. Physical component locations for PADs are also combined with the information in the NGD file.
  
  NGDAnno output is an NGA (Generic Annotated) file containing the logical design with annotations.
  
  
• The annotated design NGA file is input to one of the netlist writers (NGD2EDIF, NGD2VER, or NGD2VHDL), which translates the back-annotated information into netlist format for simulation.
  
  

In addition to back-annotating a fully routed design, the Xilinx Development System lets you back-annotate an unrouted design or create an output netlist to allow simulation of the design at different stages. For example, if you want to verify that the circuit logic is correct before you place and route your design with the Xilinx Development System tools, you can use the data in an unmapped NGD (Generic Description) design as input to the NGD2EDIF, NGD2VER, or NGD2VHDL program and run a simulation program on the resulting netlist. To simulate with components, and not route delays, you can run back-annotation on the unrouted NCD file from the MAP program.

The back-annotation flow is shown in the following figure.

Figure 18.1 Back-Annotation

You can run back-annotation by invoking NGDAnno and netlist reader programs from the UNIX or DOS command line or from the Design Manager/Flow Engine. Command line usage is explained in this chapter and in the netlist reader chapters. To use the Design Manager/Flow Engine for any of the programs, see the Design Manager/Flow Engine Guide.