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NGDAnno distributes delays, setup and hold times, and pulse widths in the physical NCD design file onto the logical design view represented in the NGD.
NGDAnno merges mapping information from the NGM file and placement, routing, and timing information from the NCD file and puts this data in an NGA (Generic Annotated) file (see the “Back-Annotation” figure).
The NGA file is input to the appropriate translation program (NGD2EDIF, NGD2VHDL, or NGDVER) used to convert the Xilinx format back to a netlist.
Note: If you make logical changes to an NCD design in the FPGA Editor, and change the functional behavior of your design, NGDAnno cannot correlate the changed objects in the physical design with the objects in the logical design. It recreates the entire NGA design from the NCD file. You get a warning indicating that the NCD file is no longer synchronized with the NGM file, and that a new NGA file has been created from the NCD file.