Terminology

Commonly used terms in the Xilinx Development System are defined in this section. Terms specific to certain Xilinx Development System modules are described in the relevant chapters.

• A device is a particular FPGA or CPLD. For example, a Xilinx XC4010E is a device.
  
  
• A site is a programmable logic element (used or unused) located within the device.
  
  
• A component is a logic configuration that will, at some point, go into a physical site. Examples of components are CLBs, IOBs, tristate buffers, pull-up resistors, and oscillators.
  
  
• A net (also called a signal) is a set of two or more component pins to be electrically connected in the finished design. A net normally consists of a driver pin and one or more load pins, but it may have more than one driver pin in certain cases. A net does not pass through a logic block, except in the case of route-throughs (routes that pass through occupied or unoccupied logic sites). The following figure shows two examples of nets. In the example, Net 1 consists of a driver pin (A) and a single load pin (B). Net 2 consists of a driver pin (A) and multiple load pins (B, C, and D). The net contains a route-through at component COMP_1.
  
  

  Figure 1.1 Net Example

• A path is an ordered set of elements identifying a logic flow pathway through a circuit. A path can consist of a single net or a grouping of related nets and components. You can have multiple paths (consisting of nets and components) between the two pins. When a component is selected as part of a path, both the input pin to the component and the output pin are included in the path.
  
  
  A path starts by including a clock-to-out delay at a synchronous element (flip flop, RAM, or latch) or from a pad. The path continues adding net delays and combinatorial delays. A path ends with a setup-to-clock delay at an asynchronous element (flip flop, RAM, or latch) or at a pad. The following figure shows a path through CLB1, CLB2, and CLB3.
  
  

  Figure 1.2 Path Example

• A bus is a grouping of related nets. For example, you can create a bus containing the nets DATA_00, DATA_01, DATA_02 and DATA_03 - nets that supply data to RAM.
  
  
• A BEL is a Basic ELement. BELs are the building blocks that make up a component (CLB or IOB) - function generators, flip-flops, carry logic, and RAMs.
  
  
• A physical macro is a logical function such as a counter that is created from a set of physical components for a specific device family. Physical macros, which are created using the FPGA Editor, are stored in files with the .nmc extension. In addition to components and nets, the file can also contain relative placement and/or routing information. A physical macro can be unplaced, partially placed, or fully placed, and it can also be unrouted, partially routed, or fully routed. Note that you cannot perform functional simulation of a physical macro. See the “Working with Physical Macros” chapter of the FPGA Editor Guide for information about physical macros.