NGD2VER Notes

Following are notes on NGD2VER.

Test Fixture File

The end of the test fixture (TV) file produced by NGD2VER contains the following commands.

#1000 $stop
// #1000 $finish

The $stop command terminates simulation from the test fixture and places the simulator in “interactive mode”. This mode allows you to view the waveforms produced or allows interaction with other programs that need the simulator open.

You can terminate the Verilog simulator as follows.

• In interactive mode, enter finish.
  
  
• To exit automatically instead of entering interactive mode, edit the test fixture file to remove or comment out the $stop line and uncomment the $finish line.
  
  

Bus Order in Verilog Files

When you compile your unit-under-test design from NGD2VER along with your test fixture, there may be mismatches on bused ports.

This problem occurs when your unit under test has top-level ports that are defined as LSB-to-MSB, as shown in the following example.

input [0:7] A;

As a result of the way your input design was converted to a netlist before it was read into the Xilinx implementation software, the Xilinx design database does not include information on how bus direction was defined in the original design. When NGD2VER writes out a structural timing Verilog description, all buses are written as MSB-to-LSB, as shown in the following example.

input [7:0] A;

If your ports are defined as LSB-to-MSB in your original input design and test fixture, there is a port mismatch when the test fixture is compiled for timing simulation. Use one of the following methods to solve this problem.

• In the test fixture, modify the instantiation of the unit under test so that all ports are defined as MSB-to-LSB for timing simulation
  
  
• Define all ports as MSB-to-LSB in your original design and test fixture. For example, enter [7:0] instead of [0:7].
  
  

Note: Bus order will be preserved if the design input file is EDIF and the buses are declared as port arrays, if you are doing logical simulation, or if you are doing back-annotation with an NGM file as input.

Verilog Identifier Naming Conventions

An identifier in a Verilog file must adhere to the following conventions. For more information see the IEEE Standard Description Language Based on the Verilog™ Hardware Description Language manual.

• Must begin with an alphabetic or underscore character (a-z, A-Z, or _)
  
  
• Can contain the characters a-z, A-Z, 0-9, _, or $
  
  
• May use any character by escaping with a backslash(\) at the beginning of the identifier, and terminating with a white space (a blank, tab, newline, or formfeed). For example, the identifier reset* is not acceptable but the identifier \reset* is acceptable.
  
  
• Can be up to 1024 characters long
  
  
• Cannot contain white space
  
  

Note: Identifiers are case sensitive.

During the name legalization process, NGD2VER writes identifiers that contain invalid characters with a leading backslash and a following white space. If you want to change this default behavior, use the -ne option described in the “-ne (Replace Invalid Characters with Underscore)” section.

Compile Scripts for Verilog Libraries

You must compile libraries for your simulation tools to recognize Xilinx components. To perform timing or post-synthesis functional HDL simulation, you must compile the SimPrim libraries. If the HDL code contains instantiated components, you must compile the UniSim or LogiBLOX libraries. If the HDL code contains instantiated components from the CORE Generator System, you must compile the COREGen behavioral models before you can perform a behavioral simulation. Refer to the CORE Generator System User Guide for more information.

To get compile scripts, go to the URLs shown in the following table.

Table 20_1 Compile Script URLs

Note: You do not need to compile libraries for Verilog-XL.