NGD2VHDL

The NGD2VHDL program translates your design into a VITAL 95 IEEE compliant VHDL file containing a netlist description of the design in terms of Xilinx simulation primitives. You can use the VHDL file to perform a back-end simulation by a VHDL simulator.

Simulation is based on SimPrims, which create simulation models using basic simulation primitives. For example, a primitive for the XC4000 dual-port RAM does not exist in the VITAL SimPrim library files. Instead, if a dual-port RAM is needed, NGD2VHDL builds a simulation model for the dual port ram out of two 16x1 RAM SimPrim primitives.

NGD2VHDL produces a VHDL file representing a design in any of the following stages.

• An unmapped design - To translate an unmapped design, the input to NGD2VHDL is an NGD file - a logical description of your design. The output from NGD2VHDL is a VHDL file containing a functional description of the design without timing information.
  
  
• A mapped, unrouted design - To translate a mapped design which has not been placed and routed, the input to NGD2VHDL is an NGA file - an annotated logical description of your design - generated from a mapped physical design. The output from NGD2VHDL is a VHDL file containing a functional description of the design, and an additional SDF (Standard Delay Format) file containing timing information. The SDF file contains component delays without routing delays.
  
  
• A routed design - To translate a design which has been placed and routed, the input to NGD2VHDL is an NGA file generated from a routed physical design. The output from NGD2VHDL is a VHDL file containing a functional description of the design and an SDF file containing both component and routing delays.
  
  

The design flow for NGD2VHDL is shown in the following figure.

Figure 21.1 NGD2VHDL Design Flow