NGD2VHDL Files

This section describes the NGD2VHDL input and output files.

Input Files

Input to NGD2VHDL can be any of the following files.

• NGA - a back-annotated logical design file containing Xilinx primitive components.
  
  
• NGD - a logical design file containing Xilinx primitive components.
  
  

Output Files

Output from NGD2VHDL consists of the following files.

• VHD file - a VITAL 95 IEEE compliant VHDL file containing the netlist information obtained from the input NGD or NGA file. This file is a simulation model and cannot be synthesized or used in any other manner than simulation. This netlist uses simulation primitives which may not represent the true implementation of the device; however, the netlist represents a functional model of the implemented design. Do not modify this file.
  
  
• SDF file - a Standard Delay Format file containing delays obtained from the input file. NGD2VHDL only generates an SDF file if the input is an NGA file, which contains timing information. The SDF file generated by NGD2VHDL is based on SDF version 2.1.
  
  
• LOG file - an optional log file created if you enter the -log option on the NGD2VHDL command line. It contains all the messages generated during the execution of NGD2VHDL.
  
  
• PIN file - an optional Cadence signal-to-pin mapping file. NGD2VHDL generates a PIN file if the input file contains routed external pins and you have specified a -pf command line option.
  
  
• Testbench file - an optional testbench file created if you enter the -tb option on the NGD2VHDL command line. The file has a .tvhd extension.