|
|
|
|
|
This section describes the NGD2VHDL command options.
By default, NGD2VHDL generates both entities and architectures for the input design. If the -a option is specified, no entities are generated and only architectures appear in the output.
The -aka option includes user-defined identifiers as comments in the VHDL netlist. This option is used if user-defined identifiers are changed because of name legalization processes in NGD2VHDL.
-ar architecture_name
The -ar option allows you to rename the architecture name generated by NGD2VHDL. The default architecture name for each entity in the netlist is STRUCTURE.
-f command_file
The -f option executes the command line arguments in the specified command_file. For more information on the -f option, see the “-f Option” section of the “Introduction” chapter.
-gp port_name
The -gp option causes NGD2VHDL to bring out the global reset signal (which is connected to all flip-flops and latches in the physical design) as a port on the top-level entity in the output VHDL file. Specifying the port name allows you to match the port name you used in the front-end. The global reset signal is discussed in the “VHDL Global Set/Reset Emulation” section.
This option is only used if the global reset net is not driven. For example, if you include a STARTUP component in an XC4000 design, you do not have to enter a -gp option, because the STARTUP component drives the global reset net.
Note: Do not use GR, GSR, PRELOAD, or RESET as port names, because these are reserved names in the Xilinx software.
-log log_file
The -log option generates a log file that contains all of the messages displayed during the execution of NGD2VHDL. Specify the name of the log file. By default, the name is ngd2vhdl.log.
-op oscillator_period
The -op option specifies the period, in nanoseconds, for the oscillator. You must specify a positive integer to stimulate the component properly. If you do not enter a value for the -op option, the default is 100 ns.
The -pf option writes out a pin file - a Cadence signal-to-pin mapping file with a .pin extension.
The -pms option forces the port names and child signal names to match.
The -r option writes out a VHDL file that retains the hierarchy in the original design as much as possible. Some loss of hierarchy may occur due to optimization. See the “Output Files” section of the “NGDAnno” chapter for more information. If loss of hierarchy occurs, NGD2VHDL produces a warning for each level of user hierarchy that is lost. Following is an example.
WARNING:NgdHelpers:182 - Hierarchical block $1I74/$1I126 has been flattened. The pins for this block will not be observable in the generated simulation model.
This option groups logic based on the original design hierarchy. To run NGD2VHDL with the -r option, you should have supplied an NGM file as input when you ran NGDAnno (see the “Input Files” section of the “NGDAnno” chapter). If you did not supply an NGM file, the NGA file produced is based on the NCD file, rather than the original design hierarchy.
The default setting (with no -r option) produces a flattened VHDL file.
-rpw roc_pulse_width
The -rpw option specifies the pulse width, in nanoseconds, for the ROC component. You must specify a positive integer to stimulate the component properly. This option is not required. By default, the ROC pulse width is set to 100ns.
The -tb option writes out a testbench file with a .tvhd extension.
The default top-level instance name within the testbench file is UUT. If you enter a -ti (Top Instance Name) option, the top-level instance name is the name specified by the -ti option.
-te top_entity_name
The -te option specifies the name of the top-level entity in the structural VHDL file produced by NGD2VHDL for timing simulation.
-ti top_instance_name
The -ti option specifies the name of the top-level instance name appearing within the output SDF file and testbench file (if produced).
The option allows you to match the top-level instance name to the name specified in your test driver VHDL file. Without this option, the SDF file generated by NGD2VHDL cannot be processed properly by VHDL simulators (for example, Model Technology vsim) for timing simulation.
If you do not enter a -ti option, the output files contain a top-level instance name of UUT.
-tp port_name
The -tp option causes NGD2VHDL to bring out the global tristate signal (which forces all FPGA outputs to the high-impedance state) as a port on the top-level entity in the output VHDL file. Specifying the port name allows you to match the port name you used in the front-end.
This option is only used if the global tristate net is not driven. For example, if you include a STARTUP component in an XC4000 design, you do not have to enter a -tp option, because the STARTUP component drives the global tristate net.
-tpw toc_pulse_width
The -tpw option specifies the pulse width, in nanoseconds, for the TOC component. You must specify a positive integer to stimulate the component properly. This option is required when you instantiate the TOC component (for example, when the global set/reset and tristate nets are sourceless in the design).
The -verbose option displays detailed VHDL processing messages when NGD2VHDL is run.
The -w option causes NGD2VHDL to overwrite the output files if they exist. By default (no -w specified) NGD2VHDL does not overwrite existing files.