Input Files

The inputs to XFLOW are a user input file, a flow file, and one or more option files.The flow file is automatically utilized when specifying a flow type - implement, tsim, config, fit, or fsim.

User Input Design File

The only required input file to XFLOW is an input design file. This design file can be an EDIF or XNF netlist, a PLD file, an NGD file, or NCD file. The following table indicates valid input files. The input file must be in one of these formats.

An input netlist file usually has a top-level module and several sub-design modules. The top-level file must be in one of the supported formats. The sub-design modules can be in other formats such as Verilog and VHDL.

Table 22_4 Valid Input Files

The UCF file allows you to specify constraints independently of an input netlist file. There can only be one UCF file per design. The UCF file will be read automatically by NGDBuild if the file resides in the same directory and has the same base name as the input design file. If the UCF file must have a different base name than an input netlist file, you can modify the -uc option for NGDBuild in an option file to read the UCF file.

All other input files are specified as arguments to the options. These option files are described in the “Option Files” section.

NGD files or NCD files can also be used as input files if you want to start the flow at an intermediate point such as MAP or PAR, rather than at the beginning stage with an EDIF or XNF netlist.

Flow Files

The following subsections describe the flow file and provide an example.

Description

All designs targeted for Xilinx devices follow a flow. A flow is a sequence of programs that are automatically invoked to implement, configure, and simulate a design. For example, to prepare an FPGA design for VHDL timing simulation, run the design through ngdbuild, map, par, ngdanno, and ngd2vhdl program flow. This sample flow requires the use of the -implement and -tsim flow types.

If you select either the -implement, -fit, -config, -tsim, or -fsim flow type, XFLOW automatically invokes one of the XIlinx flow files. The following table shows which flow files are invoked for each flow type.

Table 22_5 Xilinx Flow Files

Note: Invoked programs depend on which option file is used with each flow type. See the “Option Files” section for details about option files.

The flow file, which is ASCII format, contains the following information.

• ExportDir
  
  The directory in which to copy the outputs of individual programs in the flow. The output files are specified under the Exports option in the program block. ExportDir defaults to your working directory. You can also specify the export directory using the -ed command line option. The command line overrides any Export directory in a flow file.
  
  
• ReportDir
  
  The directory in which to copy the report files generated by the programs in the flow. The report files are specified under the Reports option in the program block. ReportDir defaults to your working directory. You can also specify the report directory using the -rd command line option. The command line overrides any Report directory in a flow file.
  
  
• Program block for each executable in the flow
  
  Each program has the following information.
  
  
  • Program program_name
    
    The name of the program, for example, ngdbuild. The Program statement is the first line of the Program block. The last line of a Program block is End Program.
    
    
  • Flag: ENABLED | DISABLED
    
    ENABLED: Only run the program if there are options in the options file.
    
    DISABLED: Do not run the program even if there are options in the options file.
    
    
  • Input:filename
    
    The name of the input file for the program. For example, for the map program, the input file is a design.ngd file.
    
    
  • Executable:executable_name
    
    A program block can be defined with or without the Executable construct. The Executable construct is useful when you want to define multiple option blocks for the same program.
    
    Case 1:
    
    If a program is defined with the Executable construct, XFLOW uses the executable_name to build the program's command line. The program's option block in the option file has the same program_name. The program_name masks the executable name so that you can define multiple option blocks for the same program allowing you to control which programs are executed
    
    For example, if you want to run TRCE, once after MAP and then again after PAR. The program name can be given any name you want. Within the block, the Executable construct will specify the correct name of the program. When XFLOW builds the command line for the program, it uses the name specified within the Executable construct. When you define the options for TRCE in the option file, there will be two entries and XFLOW will choose the correct one.
    
    Example:
    
    Program post_map_trce
    Flag: ENABLED
    Executable: trce
    Input: design_map.ncd
    Exports: design.twr
    End Program post_map_trce
    
    Case 2:
    
    If a program block is defined without the Executable construct, XFLOW uses the program_name to build the command line
    
    
  • Exports: exported_files_list
    
    List of program output files to copy into ExportDir
    
    
  • Reports: list_of_report_files
    
    List of program generated report files to copy into ReportDir
    
    
  • Variable Assignments $variable_name=value;
    
    Variable assignments can be used in the option files. During runtime, variables are substituted with their assigned values. You can use variables to specify the base name for the reports and program input or output files. The base name for functional simulation is func_sim. The base name for timing simulation is time_sim. Defined variables have global scope.
    
    
  • End Program program_name
    
    The last line of a Program block is End Program.
    
    
• User command block
  
  You can use this block to run programs or scripts between Xilinx programs. For example, if you want to run a script after map, you can add a User Command Block in the fpga.flw file as follows:
  
  

  UserCommand
  
  Cmdline: “myscript.csh”
  
  End UserCommand

  
  
  Following are some more examples of User Command Blocks:
  
  

  UserCommand
  
  Cmdline:"printenv";
  
  End UserCommand

  
  
  

  UserCommand
  
  Cmdline:"ls -ltr";
  
  End UserCommand

  
  
  

  UserCommand
  
  Cmdline:"ls -l calc.ngo"; # This works if calc.ngo                           #exists.

  
  
  

                             # If calc.ngo does not exist,                            # the ls command will                            # return a non zero
  
                             # to xflow and xflow will                            # end and give an 
  
                             # error message.

  
  
  

  End UserCommand

  
  
  

  UserCommand
  
  Cmdline:"/home/test/xflow/userscript.csh";
  
  End UserCommand

  
  
  

Following are some examples of User Command Blocks that do not work.

UserCommand

Cmdline:"ls -l *.ngo";   # doesn't handle the "*"

End UserCommand

UserCommand

Cmdline:"/bin/rm -rf $MYVAR/calc.ngo";   

# doesn't handle the "$"

End UserCommand

UserCommand

Cmdline:"if ( -e *.ngo ) /bin/rm -rf *.ngo"; 

# doesn't hamdle the "("

End UserCommand

Flow File Example

Following is an example fpga.flw file. For the most up-to-date version of the file, see the file located in $XILINX/xilinx/data.

####################################################

## FileName: fpga.flw

##

## Flow File to run Xilinx FPGA Flow

## Version: 1.0.0

## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/flowfiles/Attic/fpga.flw,v 1.1.2.2 1999/02/28 23:46:29 jayr Exp $

######################################################



ExportDir: <workdir>;        # Directory to copy program outputs

ReportDir: <workdir>;        # Directory to copy program reports



#

# Flow Info for Translator

#

Program ngdbuild

Flag : ENABLED;

Exports : <design>.ngd;

Reports : <design>.bld;

End Program ngdbuild



#

# Flow Info for Mapper

#

Program map

Flag: ENABLED;

Input: <design>.ngd;

Exports : <design>_map.ncd;

Reports : <design>_map.mrp;

End Program map



#

# Flow Info for Post Map Trace

#

Program post_map_trce

Flag: DISABLED;

Executable: trce;

Input: <design>_map.ncd;

Reports: <design>.twr;

End Program post_map_trce



#

# Flow Info for Place and Route

#

Program par

Flag : ENABLED;

Input: <design>_map.ncd;

Exports : <design>.ncd;

Reports: <design>.par <design>.dly, <design>.pad;

End Program par



#

# Flow Info for Post Par Trace

#

Program post_par_trce

Flag: ENABLED;

Executable: trce;

Input: <design>.ncd;

Reports: <design>.twr;

End Program post_par_trce



#

# Flow Info for Annotator

#

Program ngdanno

Flag: ENABLED;

Input: <design>.ncd;

End Program ngdanno



#

# Flow Info for EDIF Netlist Writer

#

Program ngd2edif

Flag: ENABLED;

Input: <design>.nga;

$input_extension = nga;

$simulation_output = time_sim;

Exports: $simulation_output.edn $simulation_output.xmm;

End Program ngd2edif



#

# Flow Info for Verilog Netlist Writer

#

Program ngd2ver

Flag: ENABLED;

Input: <design>.nga;

$input_extension = nga;

$simulation_output = time_sim;

Exports: $simulation_output.v $simulation_output.sdf, $simulation_output.tv, $simulation_output.pin;

End Program ngd2ver



#

# Flow Info for VHDL Netlist Writer

#

Program ngd2vhdl

Flag: ENABLED;

Input: <design>.nga;

$input_extension = nga;

$simulation_output = time_sim;

Exports: $simulation_output.vhd $simulation_output.sdf, $simulation_output.tvhd, $simulation_output.pin;

End Program ngd2vhdl



#

# Flow Info for Bitgen

#

Program bitgen

Flag: ENABLED;

Input: <design>.ncd;

Exports: <design>.bit, <design>.ll, <design>.msk, <design>.rbt;

Reports: <design>.bgn, <design>.drc;

End Program bitgen

#