Output Files

Development System Reference GuideChapter 22: XFLOW

Output Files

Output files from XFLOW may be generated for the following:

FPGA programming data
CPLD programming data
Annotated netlist data - These files are only generated if you run the timing simulation flows
Timing simulation data - These files are only generated if you run the timing simulation flows. They are the primary output of the back-annotation process.
Functional simulation data - These files are only generated if you
run the functional simulation flows.
Guide data
Reports

The following tables illustrate specific files that are generated for each type.

Table 22_6 FPGA Programming Data

File Type	Syntax	Location
Bitstream	design.bit	Current working directory Export directory
LL file	design.ll	Current working directory Export directory
Rawbits file	design.rbt	Current working directory Export directory

The design.ll file is generated if the -l option is set for bitgen in the option file.

The design.rbt file is created if the -b option is set for bitgen in the option file.

Table 22_7 CPLD Programming Data

File Type	Syntax	Locations
JEDEC file	design.jed	Current working directory Export directory
Design file	design.vm6	Current working directory Export directory

Note that VM6 files from the M1.5 release cannot be used as inputs to 2.1i downstream processes. You must rerun the fitter using the 2.1i software to create a new VM6 file before performing any of the following tasks:

Creating a JEDEC programming file (.jed file from the hprep program
Creating a timing report (.tim file from the taengine)
Running the Timing Analyzer
Creating a timing simulation model (.nga file from the tsim program) for input to NGD2EDIF, NGD2VHDL, or NGD2VER.

Table 22_8 Annotated Netlist Data

File Type	Syntax	Location
EDIF netlist	time_sim.edn	Current working directory Export directory
XNF netlist	time_sim.xnf	Current working directory Export directory
XMM file	time_sim.xmm	Current working directory Export directory

Annotated netlist files are only generated if you run timing simulation flows.

Table 22_9 Functional Simulation Data

File Type	Syntax	Location
EDIF simulation file	func_sim.edif	Current working directory Export directory
Verilog simulation file	func_sim.v	Current working directory Export directory
Verilog test vector file	func_sim.tv	Current working directory Export directory
VHDL simulation file	func_sim.vhd	Current working directory Export directory
VHDL test vector file	func_sim.tvhd	Current working directory Export directory

Table 22_10 Timing Simulation Data

File Type	Syntax	Location
EDIF simulation file	time_sim.edn	Current working directory Export directory
Verilog simulation file	time_sim.v	Current working directory Export directory
Verilog test vector file	time_sim.tv	Current working directory Export directory
VHDL simulation file	time_sim.vhd	Current working directory Export directory
VHDL test vector file	time_sim.tvhd	Current working directory Export directory
SDF simulation file	time_sim.sdf	Current working directory Export directory

Timing simulation data files are only generated if you run timing simulation flows. These files are the primary output of back-annotation.

Table 22_11 Guide Data

File Type	Syntax	Location
FPGA guide file	*.ncd	Current working directory Export directory
CPLD guide file	*.gyd	Current working directory Export directory

Table 22_12 Application Data Files

File Type	Syntax	Location
XFLOW log file	xflow.log	Current working directory
XFLOW script file	xflow.scr	Current working directory Export directory

XFLOW generates various reports depending on which command line options are used. The following tables indicate the types of generated reports.

Table 22_13 FPGA Report Files

Report	Flow Type	Location
Translation Report (design.bld)		Current Working Directory Report Directory
Mapping (design_map.mrp)		Current Working Directory Report Directory
Logic Level Timing (design_map.twr)		Current Working Directory Report Directory
Place and Route (design.par)	-implement	Current Working Directory Report Directory
Pad (design.pad)		Current Working Directory Report Directory
Asynchronous Delay (design.dly)		Current Working Directory Report Directory
Post Layout Timing (design.twr)		Current Working Directory Report Directory
BitGen (design.bgn)	-config	Current working directory Report directory

Table 22_14 CPLD Report Files

Report	Flow Type	Location
Translation (design.bld)		Current Working Directory Report Directory
Fitting (design.rpt)	-fit	Current Working Directory Report Directory
Post Layout Timing (design.tim)		Current Working Directory Report Directory