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This section introduces the Xilinx design entry process. You can enter a design with a schematic editor or a text-based tool. For the Alliance software, these entry methods require Xilinx-supported third-party tools, which produce a design file in some third party netlist formats. For Foundation, you access the design entry tools from the Foundation Project Manager.
Design entry begins with a design concept, expressed as a drawing or functional description. From the original design, a netlist is created, then synthesized and translated into a generic object file (NGO). This file is fed into a program called NGDBuild, which produces a logical generic database file (NGD).
The following figure illustrates the design entry process.
Figure 2.3 Design Entry FlowNote: The NGD2XNF translation program is not supported by Xilinx 2.1i software.
The following sections describe the schematic and text-based design entry methods in detail.
Schematic tools provide a graphic interface for design entry. You can use these tools to connect symbols representing the logic components in your design. You can build your design with individual gates, or you can combine gates to create functional blocks. This section focuses on ways to enter functional blocks using library elements and LogiBLOX, the logic-design/synthesis tool.
The following section discusses primitives and macros, which are the “building blocks” of component libraries.
Xilinx libraries provide primitives as well as common high-level macro functions. Primitives are basic circuit elements, such as AND and OR gates. Each primitive has a unique library name, symbol, and description. Macros contain multiple library elements, which can include primitives and other macros.
There are two types of macros you can use with Xilinx FPGAs. Soft macros, available for all FPGAs, have pre-defined functionality, but have flexible mapping, placement, and routing. Relationally placed macros (RPMs) have fixed mapping and relative placement. However, they are only available for XC4000E/X, XC5200, Spartan series, and Virtex devices.
Macros are not available for synthesis because synthesis tools have their own module generators and do not require RPMs. If you wish to override the module generation, you can instantiate LogiBLOX or CORE Generator modules. For most leading-edge synthesis tools, this does not offer an advantage unless it is for a module that cannot be inferred.
Schematics usually contain hierarchy, which is important for the following reasons.
A specific hierarchical name identifies each library element, unique block, and instance you create. For example, the last three terms in the name
/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2
might refer to the 2-input OR gate in the first instance of a multiplexer in a 4-bit counter.
Note: Xilinx strongly recommends that you name the components and nets in your design. In schematic editors, component names and net names are preserved and used by the FPGA Editor. The component names and net names are also used for back-annotation and appear in the debug and analysis tools. If you do not name your components and nets, the schematic editor automatically generates the names. For example, if left unnamed, the software might name the previous example as follows.
/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57
It can be very difficult to analyze circuits with automatically generated names, since they only have meaning for Xilinx software.
The Xilinx CORE Generator design tool delivers parameterizable cores that are optimized for Xilinx FPGAs. The library includes cores as complex as DSP (Digital Signal Processing) filters and multiplexers, and as simple as delay elements. Refer to the CORE Generator System User Guide for details.
LogiBLOX is a tool which can generate a variety of variable-sized MSI- and LSI-level design building blocks such as adders, counters, decoders, and shift registers. These modules complement the Xilinx macro libraries, which contain simpler, fixed-size logic and gate functions. LogiBLOX also integrates these modules into your design. For further information, see the LogiBLOX Guide.
Note: LogiBLOX does not currently support the Virtex and Spartan2 families of FPGAs.
Text based entry, such as modern HDLs and their associated simulators, are very powerful tools for integrated circuit designers.
Note: State machines that are created by a State Editor are converted into HDL by Xilinx tools.
A typical HDL supports a mixed-level description in which gate and netlist constructs are used with functional descriptions. This mixed-level capability enables you to describe system architectures at a very high level of abstraction, then incrementally refine a design's detailed gate-level implementation.
HDL descriptions play an important role in modern design methodology for the following reasons.
Xilinx supports HDL tools for several third-party vendors such as Synopsys, Mentor, and Viewlogic.
Before you implement your design, you may want to constrain it within certain timing or placement parameters. You can specify mapping, block placement, and timing specifications during design entry. The following sections describe these methods.
You can specify how a particular block of logic is mapped into CLBs using a CLBMAP for XC3000 FPGAs; an FMAP or HMAP for XC4000E/X and Spartan/XL FPGAs; or an FMAP or F5MAP for XC5000 FPGAs. These mapping symbols can be used in your schematic. However, if you overuse these specifications, it may be harder to route your design.
Block placement can be constrained to a specific location, to one of multiple locations, or to a location range. Locations can be specified in the schematic, with synthesis tools, or in the User Constraint File (UCF). Poor block placement can adversely affect both the placement and the routing of a design. Typically, block placement defines I/O placement. For details about placement constraints, refer to the “Placement Constraints” section in the Libraries Guide.
You can specify timing requirements for paths in your design directly in your schematic. PAR (the Xilinx FPGA Place and Route program) uses these timing specifications to achieve optimum performance when placing and routing your design. See the Timing Analyzer Guide and the Constraints Editor Guide for a detailed explanation of timing specifications. Also refer to the “Using Timing Constraints” chapter in this manual, Development System Reference Guide.
After you have entered your design, you can either simulate or implement your design. Functional simulation tests the logic in your design to determine if it works properly. You can save a lot of time during subsequent design steps if you perform functional simulation early in the design flow. For Alliance Software Series users, details on functional simulation can be found in the CAE-specific interface user guide provided with your Xilinx interface. For Foundation users, refer to the Foundation Series 2.1i User Guide.
Two netlist translation programs allow you to read netlists into the Xilinx software tools. EDIF2NGD allows you to read an EDIF 2 0 0 (Electronic Data Interchange Format) file. XNF2NGD allows you to read an XNF (Xilinx Netlist Format). In the “Design Entry Flow” figure, these programs are contained within the “Netlist Translation” block. The NGDBuild program automatically invokes these programs as needed to convert your EDIF or XNF file to the required format for the Xilinx software tools.
You can find detailed descriptions of the EDIF2NGD, XNF2NGD, and NGDBuild programs in later chapters in this book, Development System Reference Guide.