Overview

Development System Reference GuideChapter 2 : Design Flow

Overview

The design flow is a three-step process that consists of the following stages.

Design Entry - In this stage of the design flow, you create your design using a Xilinx-supported schematic editor, text-based entry (HDL), or both.
Design Implementation - By implementing to a specific Xilinx architecture, you convert the logical design file format, such as EDIF, that you created in the design entry stage into a physical file format. The physical information is contained in the NCD (Physical Description) file for FPGAs and the VM6 file for CPLDs. Then you create a bitstream file from these files and optionally program a PROM or EPROM for subsequent programming of your Xilinx device.
Design Verification - Using a gate level simulator, the Xilinx XChecker cable™, the Parallel Cable III, or MultiLINX cable, you ensure that your design meets your timing requirements and functions properly. See the Hardware User Guide for more information about Xilinx download cables and demonstration boards.

The Xilinx design flow is shown in the following figure.

Figure 2.1 Xilinx Design Flow Overview

The full design flow is an iterative process of entering, implementing, and verifying your design until it is correct and complete. The Xilinx Development System allows quick design iterations through the design flow cycle. Since Xilinx devices permit unlimited reprogramming, you do not need to discard devices when debugging your design in-circuit.

The following table defines the terms used in the “Xilinx Design Flow Overview” figure.

Table 2_1 Design Flow Terms

Term	Description
Schematic entry	Creates designs using graphic symbols
Text-based entry	Uses Hardware Description Language (HDL) or state machine editor
Optimization	Converts device-independent or behavioral logic descriptions to a form that can be efficiently implemented in a Xilinx device
Mapping	Represents a design's logic as resources of the Xilinx FPGA
Placement	Assigns design blocks created during mapping to specific locations in the FPGA
Routing	Assigns the interconnect paths in FPGAs
Fitting	Puts logic from your design into physical macrocell locations in the CPLD. Routing is performed automatically, and because of the UIM architecture, all designs are routable.
Bitstream generation	Converts a design into a bitstream that can be loaded into a Xilinx device.
Back-annotation	Associates implementation net delay information with the original nets found in the input design.
Simulation	Emulates a design`s logic and timing using input stimuli

The following figure shows the Xilinx software flow chart for designs.

Overview

Figure 2.1 Xilinx Design Flow Overview

Table 2_1 Design Flow Terms

Figure 2.2 Xilinx Software Design Flow