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Xilinx software enables you to specify precise timing requirements for your Xilinx FPGA designs. You can specify the timing requirements for any nets or paths in your design. One way of specifying path requirements is to first identify a set of paths by identifying a group of start and end points. The start and end points can be flip-flops, I/O pads, latches, or RAMs. You can then control the worst-case timing on the set of paths by specifying a single delay requirement for all paths in the set.
The primary method of specifying timing requirements is by entering them on the schematic. However, you can also specify timing requirements in constraints files (UCF and PCF). For detailed information about the constraints you can use with your schematic entry software, refer to the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide.
Once you define timing specifications and then map the design, PAR places and routes your design based on these requirements.
To analyze the results of your timing specifications, use TRACE (Timing Report and Circuit Evaluator). Refer to the “TRACE” chapter for more information.