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In the 2.1i release, the Xilinx timing tool analyzes OFFSET and FROM TO constraints that include IOB registers. The timing tool reports paths that start or end at IOB registers (including paths between components). This strategy requires the analysis of paths that internally have no length (that is, no components or connections), only a setup requirement, for pad-to-setup paths that originate at a pad and terminate at the input register within the same IOB. In the following example, the pad from the IOB pad to the input register IFD is analyzed and reported by the timing tool.
When these paths are analyzed for either TRACE or PAR, they may create timing errors that cannot be corrected because the timing requirement is less than the setup time for the I/O register. Under these conditions, TRACE always generates a timing error and PAR ceases, indicating that the place and route of the design is impossible due to existing constraints.