HDL Design Flow

The product flow for synthesis-based designs is as follows.

Module-Instantiation Tools

You can instantiate the LogiBLOX components in your HDL code to take advantage of their high-level functionality.

Express each LogiBLOX module in HDL code with a component declaration, which describes the module type, and a component instantiation, which describes how the module is connected to the other design elements.

Follow these steps to use the LogiBLOX program.

1. Invoke the Module Selector from an icon or from the command line.
   
   
2. Specify your project directory using the LogiBLOX Setup window. The default directory is your current directory.
   
   
3. Select a base module type (for example, Counter, Memory, or Shift-register, and so forth)
   
   
4. Customize the module by selecting pins and specifying attributes.
   
   
5. After completely specifying a module, click OK. Clicking OK initiates the generation of a component instantiation declaration, a behavioral model, and an implementation netlist.
   
   
6. Deposit the HDL module declaration/instantiation into your HDL design. The declaration is available as a .vei file for Verilog and a .vhi file for VHDL.
   
   
7. Complete the signal connections of the instantiated LogiBLOX module to the rest of your HDL design.
   
   
8. Behaviorally simulate your design. The HDL simulator sees the component declaration and looks for a behavioral model.
   
   Note: You may need to analyze the LogiBLOX HDL models with the appropriate CAE HDL tools for your particular simulator.
   
   
9. Implement your design by invoking the Xilinx implementation tools.
   
   
10. To simulate your design post-layout, convert your design to a timing netlist and use the back-annotation flow appropriate to your CAE tools.