|
|
|
|
|
LogiBLOX modules can be constrained by using the Floorplanner, or by attaching RLOC_ORIGIN and RLOC_RANGE constraints to them, if they are generated as RPMs (Relationally Placed Macros). Modules that can be generated as RPMs include those which contain carry logic (Accumulators, Adders, Subtracters, Counters, and Comparators), registers (Data Registers), or RAM or ROM (Memories).
You can generate Accumulators, Adders, Subtracters, and Comparators as RPMs by setting the Module Style for these modules to either ALIGNED RPM or UNALIGNED RPM. Similarly, LogiBLOX Data Registers and RAM can be generated as RPMs by setting the USE_RPM attribute to TRUE in the LogiBLOX GUI.
The modules that can be generated as RPMs are listed in the table below.
| STYLE | MODULE Type | Architecture |
| ALIGNED_RPM, UNALIGNED_RPM | Accumulators Adders/Subtracters Counters Comparators | XC4000, XC5200, Spartan XC4000, XC5200, Spartan XC4000, XC5200, Spartan XC4000, XC5200, Spartan |
| Attribute | MODULE Type | Architecture |
| USE_RPM | Data Registers RAMs | XC3000, XC4000, XC5200, Spartan XC4000, Spartan |
LogiBLOX modules are most conveniently constrained to specific locations on an FPGA using the Xilinx Floorplanner. See the Floorplanner Reference/User Guide for more information on using this tool.
LogiBLOX modules can also be constrained using RLOC_ORIGIN and RLOC_RANGE constraints on a design schematic or in a UCF file.
To constrain a LogiBLOX RPM module to a specific location in a schematic, attach an RLOC_ORIGIN property to the LogiBLOX module symbol that specifies the target location for the upper left hand corner of the RPM.
To constrain a LogiBLOX RPM module to a specific range of CLBs in a schematic, attach an RLOC_RANGE=Rr1Cc1:Rr2Cc2 property to the LogiBLOX module symbol. This property specifies the range of CLBs between rows r1 and r2 and columns c1 and c2 to which the LogiBLOX module is directed.
See the Attributes, Constraints, and Carry Logic section of the Libraries Guide for more information on specifying RLOC_ORIGIN and RLOC_RANGE constraints.
To constrain a LogiBLOX data register module into a range of CLBs in a UCF file, you must LOC every individual flip-flop in the UCF.
The flip-flops inside the LogiBLOX modules are named FLOP0, FLOP1, FLOP2, and so forth. A 20-bit data register contains FLOP0 through FLOP19.
For example, if the instance name (as opposed to the module name) of a LogiBLOX 20-bit data register module is L1, you can set the locations as follows in a UCF file.
INST L1/FLOP0 LOC=CLB_R1C1;
INST L1/FLOP1 LOC=CLB_R1C1;
INST L1/FLOP2 LOC=CLB_R2C1;
.
.
.
INST L1/FLOP19 LOC=CLB_R10C1;