PAD

Connect a Pad module to an Input/Output module to simulate the connection to a pin pad.

Figure 4.26 The Pad Module

Attributes

This attribute selects the type of I/O module to which you will connect the Pad module. Valid values are Input, Output, and Bi-Directional.

This attribute is used to tie all the pads of a symbol to pullup or pulldown resistors. If no external signal is driving an input pad or tristate output pad, and it is not pulled up/down, it will float. You can use a value of Pull Up to drive a value that tends to 1 or a value of Pull Down to drive a value that tends to 0.

This attribute is grayed out for the XC9500 and XC9500XL families.

Usage: This attribute is optional and applies only to Input or tristatable Output modules. By default, no resistor is specified.

See the XC4000E and XC4000EX sections in The Programmable Logic Data Book for timing details.

By default, a delay, representing the internal IOB delay block, is used. The delay block ensures that the data path from Pad to register, also known as the setup time, is always longer than the external clock delay.

Using the IOB delay block prevents external data from overwriting the data currently at the Data Input port of the register before that data has been clocked into the register. Delaying the source data makes it unnecessary to specify a hold time to slow down the external data.

This attribute is grayed out for the XC9500 and XC9500XL families.

Usage: This attribute is only valid for modules that include an input register. The default is to use a Delay block. Select from the following values.

• (none): This is the default. Use a Delay block to slow down the time it takes for the signal to go from the device pin (Pad pin) to the register data input pin.
  
  
• Medium Delay: This is only applicable to XC4000EX devices. It is a partial delay block within the IOB. See The Programmable Logic Data Book for more details.
  
  
• No Delay: Bypass the Delay block. If you get rid of the Delay block, ensure that the external hold time is adequate. Refer to The Programmable Logic Data Book for more information.
  
  

The slew rate of each output buffer is, by default, reduced in order to minimize power bus transients when switching non-critical signals. This reduces ground bounce when all outputs are being transitioned at the same time. See The Programmable Logic Data Book for more details.

This attribute is grayed out for the XC9500 and XC9500XL families.

Usage: This attribute is only valid for modules that include an output register. Set the Slew Rate to Fast to ensure that the fastest rate available is used for the slew rate of a critical output. The default value is Slow.

The Pad Loc attribute specifies the pin location for an I/O pad.

Unlike other LogiBLOX attributes, the LogiBLOX Pad Loc setting can be overridden by location attributes specified on the LogiBLOX symbol in the schematic.

Usage: To assign a location to a specific bit, precede the location with a bit identifier. You can assign multiple bits by using a period as a separator. For example, with a bus width of 8 bits, you could have the following assignment:

PAD_LOC=0:P44.2:P45.7:P46

This specification assigns bit 0 to pad 44, bit 2 to pad 45, and bit 7 to pad 46.

Note: Commas will not work as separators between bit assignments.