SHIFT REGISTER

The Shift Register module is multi-functional, with predefined asynchronous or synchronous pre-load, and dynamic synchronous parallel load.

Figure 4.27 The Shift Register Module

The Shift Register can be synthesized in any one of the following configurations. For examples, refer to the figures at the end of this section.

• Serial-in/serial-out shift register (FIFO or LIFO)
  
  
• Serial-in/parallel-out shift register
  
  
• Parallel-in/parallel-out shift register
  
  
• Parallel-in/serial-out shift register
  
  

You can also select the shift style of the register. The shift styles include the following.

• Logical - Data is shifted either left or right. For a left shift, the value specified by LS_IN is shifted into the LSB position. For a right shift, the value specified by MS_IN is shifted into the MSB position.
  
  
• Circular - Data is shifted in a circular pattern. For a left shift, the MSB is shifted into the LSB position. For a right shift, the LSB is shifted into the MSB position.
  
  
• Arithmetic - Data is shifted left to effectively multiply it by 2 or shifted right to effectively divide it by 2. For a left shift, a value of 0 is stuffed into the LSB. For a right shift, the Sign bit is extended if the data is signed. If the data is unsigned, a value of 0 is stuffed into the MSB.
  
  

Table 4_6 Universal Shift Register Truth Table (Logical Style)

RT/LFT	Load	Sync. Control	Clock Enable	Clock	Async. Control	Q_OUT	MS_OUT	LS_OUT
X	X	X	X	X	H	ASYNC_VAL	ASYNC_VAL MSB	ASYNC_VAL LSB
X	X	X	L		L	Qprev	Qprev MSB	Qprev LSB
X	X	H	H		L	SYNC_VAL	SYNC_VAL MSB	SYNC_VAL LSB
X	H	L	H		L	D_IN	D_IN MSB	D_IN LSB
H	L	L	H		L	Qprev/2	MS_IN	Qprev[LSB+1]
L	L	L	H		L	Qprevx2 + LS_IN	Qprev [MSB-1]	LS_IN

Figure 4.28 The Shift Register Data Flow Diagram

Input Pins

The Parallel Data from the Data Input port is loaded into the register during a Parallel Load operation on an active Clock transition.

Connections: The Data Input port is optional. When it is specified, the Load pin is also specified.

When the Parallel Load input is High, the data on the Data Input port is loaded into the Shift register on the next active Clock transition. When the Load input is Low, the counter responds to the Right/Left control input.

Connections: The Load input is automatically specified when the Data Input port is specified.

The MSB Serial Input port is only valid for a Logical style Shift Register when the shift direction is to the right. It allows you to specify a value to be stuffed into the MSB when a right shift has taken place. If no value is specified, a value of 0 is used.

The LSB Serial Input port is only valid for an Arithmetic or Logical style Shift Register when the shift direction is to the left. It allows you to specify a value to be stuffed into the LSB when a left shift has taken place. If no value is specified, a value of 0 is used.

Connections: The MSB Serial Input and LSB Serial Input ports are optional.

The Right/Left Shift control input, when High, enables the left-to-right shifting of data (from MSB to LSB); when Low, it enables the right-to-left shifting of data (from LSB to MSB). Inverting this input reverses the active High/Low definition, but does not change the MSB/LSB definitions or the shift direction.

Connections: The Right/Left pin is automatically specified when the Operation attribute is set to Right/Left.

The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute into the shift register independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value attribute. By default, the Asynchronous Value is assigned a value of zero if it is not specified. The Asynchronous Value attribute may also be specified to define the accumulator register's power-on value.

Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute is loaded into the shift register on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin and do not assign a value to the Synchronous Value attribute, a default value of 0 is used and a warning is issued.

When the Clock Enable input is High, the enabled load and shift actions take place on the next active Clock transition. When Clock Enable is Low, the register contents are unaffected by the Clock.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

If the Clock Enable input is High, the rising clock edge either loads the selected data into the register or performs a shift on the rising (positive) edge. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: The Clock input pin is always specified.

Output Pins

At least one of the output pins must be specified.

The Parallel Data output port contains the current value of the register.

Connections: If you do not specify this signal, at least one of the MSB Output or LSB Output pins must be specified.

The MSB serial-data (left-shift) output port is used for shifting or for parallel-to-serial data conversions. MS_OUT is equal to the MSB of the shift register.

Connections: This pin is optional.

The LSB serial-data (right-shift) output port is used for shifting or parallel-to-serial data conversions. LS_OUT is equal to the LSB of the shift register.

Connections: This pin is optional.

Attributes

Use the Operation attribute to specify one of the three possible types of shift registers: Right, Left, or Right/Left. If you select Right/Left, a Right/Left pin is automatically added to the module.

The shift type can be chosen from the values listed in the following table.

Usage: Shift Type defines the operation mode of the module: arithmetic, circular, or logical.

Table 4_7 Shift Types

You can use this parameter to define the encoding scheme of the data type of the Shift register. Valid values are Signed and Unsigned.

The value of the Asynchronous Value attribute defines the power-on contents of the shift register. It also defines the value to which the register returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero.

The Synchronous Value attribute defines the value to which the shift register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin.

Figure 4.29 Typical Serial-in/Parallel-out Right Shift Register

Figure 4.30 Typical Serial-in/Serial-out Right Shift Register

Figure 4.31 Typical Parallel-in/Serial-out Right Shift Register