COUNTER

The Universal Counter module generates a sequence of count values determined by the selected encoding and the status of the control inputs. The Counter module can be an up counter, down counter, or up/down counter with a predefined asynchronous or synchronous pre-load, and a dynamic synchronous parallel load.

Figure 4.8 The Counter Module

LogiBLOX counter modules can be loaded with a value applied to a bus pin or with a pre-defined constant.

Table 4_3 Universal Counter Truth Table (Binary Style)

UP/DN	Load	Sync. Control	Clock Enable	Clock	Async. Control	Q_OUT	Terminal Count
X	X	X	X	X	H	Async_Value	X1 1. An X in the Terminal Count column means this value is undefined, because Terminal Count is a function of the UP/DN and Q_OUT pins.
X	X	X	L		L	Q_OUTprev	TERM_CNTprev
X	X	H	H		L	Sync_Value	X
X	H	L	H		L	D_IN	X
H	L	L	H		L	Q+12 2. Q is the count value before the clock.	L
H	L	L	H		L	Count Limit3 3. The Count Limit value has priority over the maximum (up)-(H...H) or minimum (down)-(L...L) count values (See Count Limit attribute for restrictions).	H
L	L	L	H		L	Q-1	L
L	L	L	H		L	Count Limit	H

Input Pins

The Parallel Data from the D_IN input port is loaded into the counter during a Parallel Load operation on an active Clock transition.

Connections: The D_IN port is optional. When it is specified, the Load pin is also specified. If the module uses the LFSR Encoding, the maximum bus width for this module is 31, otherwise, the maximum bus width is 64.

When the Parallel Load input is High, the data on the D_IN input port is loaded into the counter on the next active Clock transition. When the Load input is Low, the counter responds to the Up/Down control input. In order for a Load operation to take place, Asynchronous Control and Synchronous Control must both be Low and the Clock Enable must be High.

Connections: The Load input is automatically specified when the D_IN port is specified.

The Up/Down control input controls the direction of the count on the next active Clock transition. When Up/Down is High, the counter value is increased by one; when Up/Down is Low, the counter value is decreased by one.

Connections: The Up/Down input pin is present only if the Up/Down Operation mode has been selected. Because the LFSR counter does not support down-counting, it must use the Up Operation type.

The Asynchronous Control input is a level-sensitive input. When this input is High, it loads the value assigned to the Asynchronous Value attribute (or Asynchronous Count for an LFSR counter) into the counter independently of the Clock and Clock Enable.

Connections: If you specify the Asynchronous Control pin, you can assign a value to the Asynchronous Value or Asynchronous Count attribute. By default, the attribute is assigned a value of zero if it is not specified. The Asynchronous Value and Asynchronous Control attributes may also be specified to define the counter register's power-on value.

Whenever the Synchronous Control and Clock Enable inputs are High, the value assigned to the Synchronous Value attribute (or Synchronous Count for an LFSR counter) is loaded into the counter on the next active clock transition. This input has priority over the Load input if both pins are High at the same time.

Connections: If you specify the Synchronous Control pin, you must assign a value to the Synchronous Value attribute (or Synchronous Count for an LFSR counter).

When the Clock Enable input is High, the enabled load and count actions take place on the next active Clock transition. When Clock Enable is Low, the counter contents are unaffected by the Clock.

Connections: Clock Enable is optional. Use this input when you need to disable the clock temporarily. If you do not use the Clock Enable input, the Clock is always enabled.

If the Clock Enable input is High, the rising clock edge either loads the selected data into the counter or increments/decrements the counter. The falling (negative) clock edge can be used by connecting an inverter to the Clock input.

Connections: The Clock input pin is always specified.

Output Pins

At least one of the output pins, Q_OUT or Terminal Count, must be specified.

The Counter Output pin (Q_OUT) contains the current value of the counter.

The Terminal Count output pin goes High for one clock cycle every Count Limit cycles, where Count Limit is either specified by the user or, if not specified by the user, reaches its maximum value. The maximum value of Count Limit is listed in the “Counter - Encodings” table.

• For an Up Counter, the Terminal Count is High during the cycle in which the counter reaches its maximum sequence value.
  
  
• For a Down Counter, the Terminal Count is High during the cycle in which the counter reaches its minimum sequence value, typically zero.
  
  

For example, for a 4-bit binary Up Counter with no Count Limit attribute specified, the Terminal Count is High when the counter reaches its maximum value of 1111.

The Terminal Count is not qualified with the Clock Enable. To cascade counters, AND the Terminal Count with a common Clock Enable. Refer to the “Cascading Counters with Clock Enable” figure at the end of this section for more information.

Attributes

Use the Operation attribute to specify one of the three possible types of counters: Up, Down, or Up/Down. If you select Up/Down, an Up/Down pin is automatically added to the module. Note that when the Encoding attribute is set to LFSR, the only value allowed for Operation is Up.

Style defines the implementation style (area or speed preference).

Usage: Maximum Speed is the default implementation style and is the only valid style for all counters other than Binary counters. When the Encoding attribute is set to Binary, Style can be set to any of the available values. For more information, see the “Implementation Styles” section of the “Understanding Attributes” chapter.

You can use this parameter to define the encoding of the Q_OUT port. When Encoding is set to LFSR, the only value allowed for Operation is Up, Style must be set to Maximum Speed, and the Asynchronous Count and Synchronous Count attributes are enabled instead of Asynchronous Value and Synchronous Value.

Usage: Encoding defines the count sequence of the counter. Refer to the following table for a list of available encodings.

Table 4_4 Counter - Encodings

Note: n is the width of the counter.

The Count Limit value defines the number of cycles before the counter resets to its initial value, after which the count sequence restarts. Thus, Terminal Count will be High for one cycle every Count Limit cycles. You should specify Count Limit only if the length of the count sequence is different than the MAX Count Limit associated with the counter's encoding. The allowed values for Count Limit vary depending on the counter encoding chosen.

• Binary: The Count Limit attribute values are any number between 2 and 2ⁿ-1 inclusive.
  
  
• Johnson: The only allowed Count Limit attribute values are 2n or 2n-1
  
  
• LFSR: The Count Limit attribute can be any number between 2 and 2ⁿ-1 inclusive.
  
  
• One-Hot: The Count Limit attribute may not be set.
  
  

When Count Limit is used with a Binary counter, the following applies. If counting down, the counter counts down to 0 and on the next cycle, Q_OUT goes to Count Limit. If counting up, the counter counts up to Count Limit and on the next cycle, Q_OUT goes to 0.

The behavior of a counter loaded with a value outside the range of the Count Limit (with D_IN, Sync_Val, or Async_Val) is undefined. However, Binary and Johnson counters are guaranteed to return to legal count sequences after as many as 2ⁿ (Binary) or 2n (Johnson) clock pulses.

The value of the Asynchronous Value attribute defines the power-on contents of the counter. It also defines the value to which the counter returns on assertion of the Asynchronous Control pin.

Usage: Asynchronous Value is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, its default value depends on the kind of counter you specify with the Encoding attribute. For Binary and Johnson counters the default value is zero. For One-Hot counters the default value is 1. If the Encoding attribute is set to LFSR, you cannot assign a value to the Asynchronous Value attribute.

The Synchronous Value attribute defines the value to which the register returns on assertion of the Synchronous Control pin.

Usage: Synchronous Value is available only if you specify the Synchronous Control pin. Note that when the Encoding attribute is set to LFSR, you cannot assign a value to Synchronous Value.

The Asynchronous Count attribute specifies the counter's reset state on assertion of the Asynchronous Control pin. The number specified for this attribute represents the number of transitions from the counter's initial default state. For example, if Asynchronous Count is set to 5, then the value in the counter after its first five transitions is the value assigned to the counter whenever the Asynchronous Control pin is asserted.

Usage: Asynchronous Count is always available. You can define it whether or not you use the Asynchronous Control pin. If you do not specify a value, the default value is zero. Use Asynchronous Count instead of Asynchronous Value when the Encoding attribute is set to LFSR.

The Synchronous Count attribute specifies the counter's reset state on assertion of the Synchronous Control pin. The number specified for this attribute represents the number of transitions from the counter's initial default state. For example, if Synchronous Count is set to 5, then the value in the counter after its first five transitions is the value assigned to the counter whenever the Synchronous Control pin is asserted.

Usage: Synchronous Count is available only if you specify the Synchronous Control pin. Use Synchronous Count instead of Synchronous Value when the Encoding attribute is set to LFSR.

Counter Encoding Features and Selection Criteria

Each of the four counter encodings has benefits and limitations that are determined by the available chip resources. The “Counter - Encodings” table lists the criteria that can be used to select the appropriate encoding for each application. A brief description of each encoding follows.

The Binary Counter produces a predictable binary output pattern and is the recommended encoding for Up/Down counter applications. It is used to produce sequences for address generation, binary arithmetic, or related applications. Variations in count modulo are set by using the Count Limit attribute or Synchronous Load capability. The Binary Counter is synthesized to take advantage of fast carry logic on the XC4000 and XC5200 families. For a binary encoding, the width of the signal connected to D_IN and Q_OUT can be >= log₂ Count Limit.

When the Style is set to Maximum Speed, the bus width determines the implementation of the Binary Counter in the XC4000EX family. If the bus width is greater than four bits, the counter is implemented using carry logic. If the bus width is four bits or less, gates are used in the implementation.

The Johnson Counter is the fastest encoding available. This encoding is used to produce very fast state machines and glitchless decoders. It supports Asynchronous and Synchronous Loads, but the loaded values must correspond to the normal count sequence to maintain predictable output results. Valid values for the Synchronous Value and Asynchronous Value attributes include:

• All zeros
  
  
• All ones
  
  
• Zeros followed by ones
  
  
• Ones followed by zeros
  
  

For example, a 3-bit Johnson up counter sequence is as follows.

0 0 0
1 0 0
1 1 0
1 1 1
0 1 1
0 0 1

One bit in the count sequence changes per clock cycle if the default Count Limit=2n is used. If Count Limit is assigned by the user to
2n-1, then 2 bits will change during one clock cycle in the middle of the sequence as in the following 3-bit example with Count Limit=5.

0 0 0
1 0 0
1 1 0
0 1 1
0 0 1

The LFSR counter is fast and uses chip resources efficiently. It can be configured to support any Count Limit value, but the output pattern is difficult to determine. It is used for frequency division, such as the CLK_DIV module, modulo x counting, and pseudo-random-pattern generation. It does not support down counting. The width of the LFSR counter must be between 2 and 31 bits. If more bits are needed, several LFSR counters can be cascaded. Refer to the “Cascading Counters” section section for examples of cascaded counters.

In an LFSR counter, the MSB bit toggles first.

Note: Specifying the Asynchronous Count and Count Limit attributes may result in unexpected behavior in an LFSR counter. For example, if Asynchronous Count is set to 2 and Count Limit is set to 5, at startup the counter should start with the second cycle and TERM_CNT should go high at the fifth cycle, that is, after three rising clock edges (this is how a Binary counter works). But TERM_CNT goes high after two rising clock edges. After that, it goes high every fifth rising edge. This behavior occurs because a Count Limit of 5 specifies a Binary counter with six states (0 to 5), while it specifies an LFSR counter with five states.

In this encoding, only one bit is High at a time. Use this encoding to enable a selection of mutually exclusive actions. Do not specify the Count Limit attribute for this encoding.

• An up-counter has the “1” in the least index bit at reset and shifts it one bit toward the greatest index bit at each clock cycle, returning it to the least index bit after n cycles. Terminal Count is High when the high bit is the highest index bit.
  
  
• A down-counter has the same initial state, but shifts toward the least bit and has Terminal Count High when the high bit is the least index bit.
  
  

Valid One Hot values for loading or assigning to the Asynchronous Value and Synchronous Value attributes may have only a single bit set. Ensure that neither multiple set bits nor no set bits are ever loaded into a One Hot counter, because this will result in improper count behavior.

Cascading Counters

If you need to cascade LogiBLOX counters, exercise caution if the counter module has a Clock Enable control signal. The Terminal Count outputs of all LogiBLOX counters do not incorporate the input Clock Enable control. As a result, the Clock Enable control signal of the first counter in the cascade chain needs to be ANDed with the Terminal Count of each counter. This ANDed term should then be used to enable the next counter in the chain.

Figure 4.9 Cascading Counters with Clock Enable

LogiBLOX counter chains which do not have an initial Clock Enable control signal can be implemented simply by connecting the Terminal Count from each stage to the subsequent stage.