X74_174

6-Bit Data Register with Active-Low Asynchronous Clear

The active-Low asynchronous clear input (CLR), when Low, overrides the clock and resets the six data outputs (Q6 - Q1) Low. When CLR is High, the data on the six data inputs (D6 - D1) is transferred to the corresponding data outputs on the Low-to-High clock (CK) transition.

Inputs			Outputs
CLR	D6 - D1	CK	Q6 - Q1
0	X	X	0
1	D6 - D1		d6 - d1
dn = state of referenced input one setup time prior to active clock transition

Figure 11.30 X74_174 Implementation XC3000, XC4000E, XC4000X, XC5200, XC9000, Spartan, SpartanXL