X74_194

4-Bit Loadable Bidirectional Serial/Parallel-In Parallel-Out Shift Register

X74_194 is a 4-bit shift register with shift-right serial input (SRI), shift-left serial input (SLI), parallel inputs (D - A), parallel outputs (QD - QA), two control inputs (S1, S0), and active-Low asynchronous clear (CLR). The shift register performs the following functions.

Clear	When CLR is Low, all other inputs are ignore and outputs QD - QA go to logic state zero.
Load	When S1 and S0 are High, the data on inputs D -A is loaded into the corresponding output bits QD -QA during the Low-to-High clock (CK) transition.
Shift Right	When S1 is Low and S0 is High, the data is to the next-highest bit position (right) as new data is loaded into QA(SRIQA,QAQB, QBQC, and so forth).
Shift Left	When S1 is High and S0 is Low, the data is shifted to the next-lowest bit position (left) as new data is loaded into QD (SLIQD,QDQC,QCQB, and so forth).

Registers can be cascaded by connecting the QD output of one stage to the SRI input of the next stage, the QA output of one stage to the SLI input of the next stage, and connecting clock, S1, S0, and CLR inputs in parallel.

Inputs							Outputs
CLR	S1	S0	SRI	SLI	A - D	CK	QA	QB	QC	QD
0	X	X	X	X	X	X	0	0	0	0
1	0	0	X	X	X	X	No Chg	No Chg	No Chg	No Chg
1	1	1	X	X	A - D		a	b	c	d
1	0	1	SRI	X	X		sri	qa	qb	qc
1	1	0	X	SLI	X		qb	qc	qd	sli
Lowercase letters represent state of referenced input or output one setup time prior to active clock transition

Figure 11.31 X74_194 Implementation XC3000, XC4000E, XC4000X, XC5200, XC9000, Spartan, SpartanXL