|
|
|
|
|
Xilinx recommends that you always connect input pins in your schematics. This ensures that front end simulation functionally matches back end timing simulation. If an input pin is left unconnected, mapper errors may result.
If an output pin is left unconnected in your schematic, the corresponding function is trimmed. If the component has only one output, the entire component is trimmed. If the component has multiple outputs, the portion that drives the output is trimmed. As an example of the latter case, if the overflow pin (OFL) in an adder macro is unconnected, the logic that generates that term is trimmed, but the rest of the adder is retained (assuming all of the sum outputs are connected).