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| Element | XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
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| AND2, AND2B1, AND2B2, AND3, AND3B1, AND3B2, AND3B3, AND4, AND4B1, AND4B2, AND4B3, AND4B4 | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive | Primitive |
| AND5, AND5B1, AND5B2, AND5B3, AND5B4, AND5B5 | Primitive | Primitive | Primitive | Macro | Primitive | Primitive | Primitive | Primitive | Primitive |
| AND6, AND7, AND8, AND9 | Macro | Macro | Macro | Macro | Primitive | Macro | Macro | Macro | Macro |
Figure 3.23 AND Gate RepresentationsThe AND function is performed in the Configurable Logic Block (CLB) function generators for XC3000, XC4000E, XC4000X, XC5200, Spartan, and SpartanXL.
AND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. AND functions of six to nine inputs are available with only non-inverting inputs. To make some or all inputs inverting, use external inverters. Because each input uses a CLB resource in FPGAs, replace functions with unused inputs with functions having the appropriate number of inputs.
Refer to “AND12, 16” for information on additional AND functions for the XC5200, Spartan2, and Virtex.
Figure 3.24 AND5 Implementation XC5200Figure 3.25 AND8 Implementation XC3000Figure 3.26 AND8 Implementation XC4000E, XC4000X, Spartan, SpartanXLFigure 3.27 AND8 Implementation XC5200Figure 3.28 AND8 Implementation Spartan2, Virtex