Chapter 5

Design Elements (F5MAP to FTSRLE)

This chapter describes design elements included in the Unified Libraries. The elements are organized in alphanumeric order with all numeric suffixes in ascending order.

The library applicability table at the beginning of an element description identifies how the element is implemented in each library as follows.

• Primitive
  
  A primitive is a basic building block that cannot be broken up into smaller components.
  
  
• Macro
  
  A macro is constructed from primitives. Macros whose implementations contain relative location constraint (RLOC) information are known as Relationally Placed Macros (RPMs).
  
  Schematics for macro implementations are included at the end of the component description. Schematics are included for each library if the macro implementation differs. Design elements with bused or multiple I/O pins (2-, 4-, 8-, 16-bit versions) typically include just one schematic - generally the 8-bit version. When only one schematic is included, implementation of the smaller and larger elements differs only in the number of sections. In cases where an 8-bit version is very large, an appropriate smaller element serves as the schematic example.
  
  
• N/A
  
  Certain design elements are not available in all libraries because they cannot be accommodated in all device architectures. These are marked as N/A (Not Available).
  
  

Refer to the “Applicable Architectures” section of the “Xilinx Unified Libraries” chapter for information on the specific architectures supported by each of the following libraries: XC3000 Library, XC4000E Library, XC4000X Library, XC5200 Library, XC9000 Library, Spartan Library, SpartanXL Library, Spartan2 Library, and Virtex Library.

Note: Wherever XC4000 is used, the information applies to all architectures supported by the XC4000E and XC4000X libraries. Wherever Spartans is used, the information applies to all architectures supported by the Spartan, SpartanXL, and Spartan2 libraries.