FDRE

D Flip-Flop with Clock Enable and Synchronous Reset

FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Inputs				Outputs
R	CE	D	C	Q
1	X	X		0
0	0	X	X	No Chg
0	1	1		1
0	1	0		0

Figure 5.21 FDRE Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL

Figure 5.22 FDRE Implementation XC9000