Libraries GuideChapter 5: Design Elements (F5MAP to FTSRLE)
FDRE_1
D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| N/A
| N/A
| N/A
| N/A
| N/A
| N/A
| Primitive
| Primitive
|
FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the High-to-Low clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex and Spartan2 simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2 or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
R
| CE
| D
| C
| Q
|
|---|
1
| X
| X
| 
| 0
|
0
| 0
| X
| X
| No Chg
|
0
| 1
| 1
|
| 1
|
0
| 1
| 0
|
| 0
|
