FDSR

D Flip-Flop with Synchronous Set and Reset

FDSR is a single D-type flip-flop with data (D), synchronous reset (R) and synchronous set (S) inputs and data output (Q). When the set (S) input is High, it overrides all other inputs and sets the Q output High during the Low-to-High clock transition. (Set has precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset, output Low, on the Low-to-High clock transition. Data on the D input is loaded into the flip-flop when S and R are Low on the Low-to-High clock transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP symbol.

Inputs				Outputs
S	R	D	C	Q
1	X	X		1
0	1	X		0
0	0	1		1
0	0	0		0

Figure 5.30 FDSR Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL

Figure 5.31 FDSR Implementation XC9000