FDSRE

D Flip-Flop with Synchronous Set and Reset and Clock Enable

FDSRE is a single D-type flip-flop with synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, it overrides all other inputs and sets the Q output High during the Low-to-High clock transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low during the Low-to-High clock transition. Data is loaded into the flip-flop when S and R are Low and CE is High during the Low-to-high clock transition. When CE is Low, clock transitions are ignored.

The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP symbol.

Inputs					Outputs
S	R	CE	D	C	Q
1	X	X	X		1
0	1	X	X		0
0	0	0	X	X	No Chg
0	0	1	1		1
0	0	1	0		0

Figure 5.32 FDSRE Implementation XC3000, XC4000E, XC4000X, XC5200, Spartan, SpartanXL

Figure 5.33 FDSRE Implementation XC9000