XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
---|---|---|---|---|---|---|---|---|
N/A | N/A | N/A | N/A | N/A | N/A | N/A | Primitive | Primitive |
IBUFG and its variants (listed below) are dedicated input buffers for connecting to the clock buffer (BUFG) or CLKDLL. The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the I/O interface standard used by the component. For example, IBUFG_CTT is an input buffer that uses the CTT I/O- signaling standard.
The Xilinx implementation software converts each BUFG to an appropriate type of global buffer for the target PLD device. The IBUFG output can only be connected to the CLKIN input of a CLKDLL or to the input of a BUFG. The IBUFG can only be driven by an IPAD.
The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectI/O buffer components. Refer to the SelectI/O Usage Rules section under the IBUF_selectIO section for information on using these components.
Component | I/O Standard | VREF |
---|---|---|
IBUFG | LVTTL | N/A |
IBUFG_LVCMOS2 | LVCMOS2 | N/A |
IBUFG_PCI33_3 | PCI33_3 | N/A |
IBUFG_PCI33_5 | PCI33_5 | N/A |
IBUFG_PCI66_3 | PCI66_3 | N/A |
IBUFG_GTL | GTL | 0.80 |
IBUFG_GTLP | GTL+ | 1.00 |
IBUFG_HSTL_I | HSTL_I | 0.75 |
IBUFG_HSTL_III | HSTL_III | 0.90 |
IBUFG_HSTL_IV | HSTL_IV | 0.75 |
IBUFG_SSTL2_I | SSTL2_I | 1.10 |
IBUFG_SSTL2_II | SSTL2_II | 1.10 |
IBUFG_SSTL3_I | SSTL3_I | 0.90 |
IBUFG_SSTL3_II | SSTL3_II | 1.50 |
IBUFG_CTT | CTT | 1.50 |
IBUFG_AGP | AGP | 1.32 |