IFD, 4, 8, 16

Single- and Multiple-Input D Flip-Flops

The IFD D-type flip-flop is contained in an input/output block (IOB), except for XC5200 and XC9000. The input (D) of the flip-flop is connected to an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, which synchronizes data entering the chip. The data on input D is loaded into the flip-flop during the Low-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin.

The flip-flops are asynchronously cleared with Low outputs when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

For information on legal IFD, IFD_1, ILD, and ILD_1 combinations, refer to the “ILD, 4, 8, 16” section.

Inputs		Outputs
D	C	Q
0		0
1		1

Figure 6.4 IFD Implementation XC4000E, XC4000X, Spartan, SpartanXL

Figure 6.5 IFD Implementation XC5200, Spartan2, Virtex

Figure 6.6 IFD Implementation XC9000

Figure 6.7 IFD8 Implementation XC3000, XC4000E, XC4000X, XC5200, XC9000, Spartan, SpartanXL, Spartan2, Virtex